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| 1. description the M306V5ME-XXXSP and m306v5eesp are single-chip microcomputers using the high-performance silicon gate cmos process using a m16c/60 series cpu core and are packaged in a 64-pin plastic molded sdip. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, they are capable of executing instructions at high speed. they also feature a built-in osd display function and data slicer, making them ideal for controlling tv with a closed caption decoder. the features of the m306v5eesp are similar to those of the M306V5ME-XXXSP except that this chip has a built-in prom which can be written electrically. 1.1 features ? memory size ........................................ M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 2 rev. 1.0 ------table of contents------ 2.16.18 scan mode ................................ 219 2.16.19 r, g, b signal output control ... 219 2.16.20 osd reserved register ........... 220 2.17 programmable i/o ports .................... 221 3. usage precaution .............................. 239 3.1 timer a (timer mode) ........................... 239 3.2 timer a (event counter mode) ............. 239 3.3 timer a (one-shot timer mode) ............ 239 3.4 timer a (pulse width modulation mode) .... 239 3.5 timer b (timer mode, event counter mode) ..... 240 3.6 timer b (pulse period/pulse width measurement mode) ........................... 240 3.7 a-d converter ...................................... 240 3.8 stop mode and wait mode .................. 240 3.9 interrupts .............................................. 241 3.10 built-in prom version ....................... 242 4. item to be submitted when ordering masked rom version ......................... 243 5. electrical characteristics .......... 244 5.1 absolute maximum ratings ................. 244 5.2 recommended operating conditions .. 245 5.3 electrical characteristics ..................... 246 5.4 a-d conversion characteristics ........... 247 5.5 d-a conversion characteristics ........... 247 5.6 analog r, g, b output characteristics ....... 247 5.7 timing requirements ........................... 248 5.8 switching characteristics ..................... 250 6. mask rom confirmation form ....... 251 7. mark specification form ................ 255 8.one time prom version m306v5eesp marking ........................... 256 9. package outline ................................. 257 1. description .............................................. 1 1.1 features ................................................... 1 1.2 applications ............................................. 1 1.3 pin configuration ..................................... 3 1.4 block diagram ......................................... 4 1.5 performance outline ................................ 5 2. operation of functional blocks .. 10 2.1 memory .................................................. 10 2.2 central processing unit (cpu) .............. 16 2.3 reset ..................................................... 19 2.4 single-chip mode ................................... 23 2.5 clock generating circuit ........................ 27 2.6 protection ............................................... 35 2.7 overview of interrupt ............................. 36 2.8 watchdog timer .................................... 56 2.9 dmac .................................................... 58 2.10 timer .................................................... 68 2.11 serial i/o .............................................. 88 2.12 a-d converter .................................... 138 2.13 d-a converter .................................... 153 2.14 data slicer ......................................... 155 2.15 h sync counter .................................. 165 2.16 osd function .................................... 166 2.16.1 triple layer osd ........................ 172 2.16.2 display position .......................... 174 2.16.3 dot size ...................................... 178 2.16.4 clock for osd ............................. 179 2.16.5 field determination display ........ 180 2.16.6 memory for osd ......................... 182 2.16.7 character color .......................... 195 2.16.8 character background color ...... 195 2.16.9 out1, out2 signals .................. 200 2.16.10 attribute .................................... 201 2.16.11 automatic solid space function ..... 206 2.16.12 particular osd mode block ...... 207 2.16.13 multiline display ........................ 209 2.16.14 sprite osd function ............. 210 2.16.15 window function ...................... 213 2.16.16 blank function .......................... 214 2.16.17 raster coloring function .......... 217 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 3 rev. 1.0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 r e s e t p 7 1 / r x d 2 / s c l 1 p 1 0 1 / v s y n c p 1 0 0 / h s y n c t v s e t b a v c c c v i n v h o l d h l f p 9 4 / d a 1 / s c l 3 x o u t v s s x i n v c c o s c 1 o s c 2 p 8 2 / i n t 0 o u t 1 p 7 4 / t a 2 o u t p 7 2 / c l k 2 / s c l 2 p 7 0 / t x d 2 / s d a 1 p 0 0 p 0 1 p 0 2 p 0 3 p 0 4 p 0 5 p 0 6 p 2 5 p 2 7 p 3 1 p 3 3 / i n t 1 p 3 4 / h c 0 p 3 5 / h c 1 p 3 6 / a n 0 p 4 0 / a n 2 p 4 1 / a n 3 p 5 0 p 5 2 p 5 3 p 5 5 / c l k 0 p 3 7 / a n 1 p 9 3 / d a 0 / s d a 3 p 9 0 / t b 0 i n c n v s s o u t 2 p 7 6 / t a 3 o u t p 0 7 p 2 0 p 2 3 p 2 4 2 2 2 3 2 4 2 5 2 6 4 3 4 2 4 1 4 0 3 9 m 3 0 6 v 5 m e - x x x s p m 3 0 6 v 5 e e s p r p 6 7 / s d a 2 g p 6 3 / t x d 0 b p 6 2 / r x d 0 2 7 2 8 2 9 3 0 3 1 3 2 3 8 3 7 3 6 3 5 3 4 3 3 p 2 1 p 2 2 p 2 6 p 3 0 p 3 2 p 4 2 / a n 4 p 4 3 / a n 5 1.3 pin configuration figure 1.3.1 shows the pin configuration (top view). pin configuration (top view) package: 64p4b figure 1.3.1 pin configuration (top view) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 4 rev. 1.0 1.4 block diagram figure 1.4.1 is a block diagram. figure 1.4.1 block diagram t i m e r t i m e r t a 0 ( 1 6 b i t s ) t i m e r t a 1 ( 1 6 b i t s ) t i m e r t a 2 ( 1 6 b i t s ) t i m e r t a 3 ( 1 6 b i t s ) t i m e r t a 4 ( 1 6 b i t s ) t i m e r t b 0 ( 1 6 b i t s ) t i m e r t b 1 ( 1 6 b i t s ) t i m e r t b 2 ( 1 6 b i t s ) i n t e r n a l p e r i p h e r a l f u n c t i o n s i / o p o r t s p o r t p 0 8 p o r t p 2 8 p o r t p 3 8 p o r t p 4 4 p o r t p 5 4 p o r t p 6 3 5 1 p o r t p 8 p o r t p 7 w a t c h d o g t i m e r ( 1 5 b i t s ) d m a c ( 2 c h a n n e l s ) d - a c o n v e r t e r ( 8 b i t s x 2 c h a n n e l s ) m 1 6 c / 6 0 s e r i e s 1 6 - b i t c p u c o r e r 0 l r 0 h r 1 hr 1 l r 2 r 3 a 0 a 1 f b r 0 l r 0 h r 1 hr 1 l r 2 r 3 a 0 a 1 f b r e g i s t e r s i s p u s p s t a c k p o i n t e r v e c t o r t a b l e i n t b m u l t i p l i e r 3 2 p o r t p 1 0 p o r t p 9 m e m o r y r o m 1 9 2 k r a m 5 k s b f l g p c p r o g r a m c o u n t e r a - d c o n v e r t e r o s d s y s t e m c l o c k g e n e r a t o r x i n x o u t d a t a s l i c e r u a r t / c l o c k s y n c h r o n o u s s i / o h s y n c c o u n t e r m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 0 u a r t / c l o c k s y n c h r o n o u s s i / o m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 5 rev. 1.0 item performance number of basic instructions 91 instructions shortest instruction execution time 100 ns(f(x in )=10 mhz) memory rom 192k bytes size ram 5k bytes osd rom 61k bytes osd ram 2.2k bytes i/o port p0, p2 to p10 8 bits 5 3, 5 bits 5 1, 4 bits 5 2, 3 bits 5 2, 2 bits 5 1, 1 bit 5 1 multifunction ta0, ta1, ta2, ta3, ta4 16 bits 5 5 timer tb0, tb1, tb2 16 bits 5 3 serial i/o uart0 1 unit: uart or clock synchronous uart2 1 unit: uart or clock synchronous multi-master i 2 c-bus interface 0 1 unit (2 channels) multi-master i 2 c-bus interface 1 1 unit (1 channels) a-d converter 8 bits 5 6 channels d-a converter 8 bits 5 2 channels dmac 2 channels (trigger: 23 sources) osd function triple layer, 890 kinds of fonts, 42 character 5 16 lines data slicer 32-bit buffer h sync counter 8 bits 5 2 channels watchdog timer 15 bits 5 1 (with prescaler) interrupt 21 internal and 3 external sources, 4 software sources, 7 levels clock generating circuit 2 built-in clock generation circuits power source voltage 4.5 v to 5.5v (f(x in ) = 10 mhz) power consumption 250 mw i/o i/o withstand voltage 5 v characteristics output current 5 ma operating ambient temperature C10 o c to 70 o c device configuration cmos high performance silicon gate package 64-pin plastic molded sdip table 1.5.1 performance outline 1.5 performance outline table 1.5.1 is a performance outline. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 6 rev. 1.0 figure 1.5.1 type no., memory size, and package currently supported products are listed below. table 1.5.2 list of supported products note: since eprom version is for development support tool (for evaluation), do not use for mass produc- tion. p a c k a g e t y p e : s p : p a c k a g e6 4 p 4 b s s : p a c k a g e6 4 s 1 b r o m n o . o m i t t e d f o r o n e t i m e p r o m v e r s i o n a n d e p r o m v e r s i o n r o m c a p a c i t y : e : 1 9 2 k b y t e s m e m o r y t y p e : m : m a s k r o m v e r s i o n e : o n e t i m e p r o m v e r s i o n o r e p r o m v e r s i o n t y p e n o . m 3 0 6 v 5 m e x x x s p m 1 6 c / 6 v g r o u p m 1 6 c f a m i l y s h o w s r a m c a p a c i t y , p i n c o u n t , e t c ( t h e v a l u e i t s e l f h a s n o s p e c i f i c m e a n i n g ) r a m c a p a c i t y r o m c a p a c i t y p a c k a g e t y p e r e m a r k s t y p e n o m 3 0 6 v 5 m e - x x x s p5 k b y t e s m a s k r o m v e r s i o n o n e t i m e p r o m v e r s i o n m 3 0 6 v 5 e e s p1 9 2 k b y t e s6 4 p 4 b 1 9 2 k b y t e s 5 k b y t e s 6 4 p 4 b e p r o m v e r s i o n m 3 0 6 v 5 e e s s1 9 2 k b y t e s6 4 s 1 b 5 k b y t e s M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 7 rev. 1.0 1.5.1 as for m16c/6v (64-pin version) group m16c/6v (64-pin version) group is packaged in a 64-pin plastic molded sdip. note that the number of pins is reduced when it is compared with a 100-pin package product. (1) m16c/6v (64-pin version) group supports only the shingle-chip mode. it does not support the memory expansion and the microprocessor modes. (2) be sure to initialize in the sequence below immediately after reset release. set osd reserved register i (i = 1 to 4) to the specified values. set each reserved bit of the port pi direction register, the port pi register, and pull-up control register i to the specified values. a set port reserved register i (i = 1 to 3) to the specified values. ? set other reserved registers and each reserved bit of other registers to the specified values. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 8 rev. 1.0 table 1.5.3 pin description (1) v c c , v s s c n v s s x i n x o u t a v c c p 0 0 t o p 0 7 s i g n a l n a m e p o w e r s u p p l y i n p u t c n v s s r e s e t i n p u t c l o c k i n p u t c l o c k o u t p u t a n a l o g p o w e r s u p p l y i n p u t i / o p o r t p 0 s u p p l y 4 . 5 v t o 5 . 5 v t o t h e v c c p i n . s u p p l y 0 v t o t h e v s s p i n . f u n c t i o n c o n n e c t t h i s p i n t o t h e v s s p i n . a l o n t h i s i n p u t r e s e t s t h e m i c r o c o m p u t e r . t h e s e p i n s a r e p r o v i d e d f o r t h e m a i n c l o c k g e n e r a t i n g c i r c u i t . c o n n e c t a c e r a m i c r e s o n a t o r o r c r y s t a l b e t w e e n t h e x i n a n d t h e x o u t p i n s . to u s e a n e x t e r n a l l y d e r i v e d c l o c k , i n p u t i t t o t h e x i n p i n a n d l e a v e t h e x o u t p i n o p e n . t h i s p i n i s a p o w e r s u p p l y i n p u t f o r t h e a - d c o n v e r t e r . c o n n e c t t h i s p i n t o v c c . t h i s i s a n 8 - b i t c m o s i / o p o r t . i t h a s a n i n p u t / o u t p u t p o r t d i r e c t i o n r e g i s t e r t h a t a l l o w s t h e u s e r t o s e t e a c h p i n f o r i n p u t o r o u t p u t i n d i v i d u a l l y . w h e n s e t f o r i n p u t , t h e u s e r c a n s p e c i f y i n u n i t s o f f o u r b i t s v i a s o f t w a r e w h e t h e r o r n o t t h e y a r e t i e d t o a p u l l - u p r e s i s t o r . p i n n a m e i n p u t i n p u t i n p u t o u t p u t i n p u t / o u t p u t i / o t y p e p 2 0 t o p 2 7 p 3 0 t o p 3 7 p 4 0 t o p 4 3 i / o p o r t p 2 i / o p o r t p 3 i / o p o r t p 4 t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 0 . t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 0 . p i n s i n t h i s p o r t f u n c t i o n a s e x t e r n a l i n t e r r u p t p i n , h s y n c c o u n t e r i / o p i n s , a n d a - d c o n v e r t e r i n p u t p i n s a s s e l e c t e d b y s o f t w a r e . t h i s i s a n 8 - b i t i / o p o r t e q u i v a l e n t t o p 0 . p i n s i n t h i s p o r t f u n c t i o n a s a - d c o n v e r t e r i n p u t p i n s a s s e l e c t e d b y s o f t w a r e . i n p u t / o u t p u t i n p u t / o u t p u t i n p u t / o u t p u t r e s e t i / o p o r t p 5i n p u t / o u t p u t i n p u t / o u t p u t i / o p o r t p 6 p 5 0 , p 5 2 , p 5 3 , p 5 5 p 6 2 , p 6 3 , p 6 7 t h i s i s a 4 - b i t i / o p o r t e q u i v a l e n t t o p 0 . p 5 7 i n t h i s p o r t f u n c t i o n s a s u a r t 0 i / o p i n a s s e l e c t e d b y s o f t w a r e . t h i s i s a 3 - b i t i / o p o r t e q u i v a l e n t t o p 0 . p i n s i n t h i s p o r t a l s o f u n c t i o n a s u a r t 0 a n d m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 0 i / o p i n s a s s e l e c t e d b y s o f t w a r e . i n p u t / o u t p u t i n p u t / o u t p u t i n p u t / o u t p u t i / o p o r t p 7 i / o p o r t p 8 i / o p o r t p 9 p 7 0 t o p 7 2 , p 7 4, p 7 6 p 8 2 p 9 0 , p 9 3 , p 9 4 t h i s i s a 5 - b i t i / o p o r t e q u i v a l e n t t o p 0 ( p 7 0 a n d p 7 1 a r e n - c h a n n e l o p e n - d r a i n o u t p u t ) . p i n s i n t h i s p o r t a l s o f u n c t i o n a s t i m e r s a 2 a n d a 3 , u a r t 2 , m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 0 i / o p i n s a s s e l e c t e d b y s o f t w a r e . t h i s i s a n 3 - b i t i / o p o r t e q u i v a l e n t t o p 0 . p i n s i n t h i s p o r t a l s o f u n c t i o n a s t i m e r b 0 i n p u t p i n , d - a c o n v e r t e r o u t p u t p i n s , a n d m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 1 i / o p i n s a s s e l e c t e d b y s o f t w a r e . p 8 2 i s i / o p o r t w i t h t h e s a m e f u n c t i o n s a s p 0 . p 8 2 c a n b e m a d e t o f u n c t i o n a s t h e i / o p i n f o r t h e i n p u t p i n s f o r e x t e r n a l i n t e r r u p t s a s s e l e c t e d b y s o f t w a r e . M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 9 rev. 1.0 table 1.5.4 pin description (continued) (2) s i g n a l n a m ef u n c t i o n p i n n a m e i / o t y p e i n p u t / o u t p u t i / o p o r t p 1 0 p 1 0 0 , p 1 0 1 t h i s i s a 2 - b i t i / o p o r t e q u i v a l e n t t o p 0 . p i n s i n t h i s p o r t a l s o f u n c t i o n a s a i n p u t p i n s f o r o s d f u n c t i o n a s s e l e c t e d b y s o f t w a r e . r , g , b o s c 1 o s c 2 c v i n v h o l d h l f t v s e t b o s d o u t p u t c l o c k i n p u t f o r o s d c l o c k o u t p u t f o r o s d i / o f o r d a t a s l i c e r t e s t i n p u t o u t p u t i n p u t o u t p u t i n p u t i n p u t i n p u t t h e s e a r e o s d o u t p u t p i n s ( a n a l o g o u t p u t ) . t h i s i s a n o s d c l o c k i n p u t p i n . t h i s i s a n o s d c l o c k o u t p u t p i n . i n p u t c o m p o s i t e v i d e o s i g n a l t h r o u g h a c a p a c i t o r . c o n n e c t a c a p a c i t o r b e t w e e n v h o l d a n d v s s . c o n n e c t a f i l t e r u s i n g o f a c a p a c i t o r a n d a r e s i s t o r b e t w e e n h l f a n d v s s . t h i s i s a t e s t i n p u t p i n . f i x i t t o l . o u t 1 , o u t 2 t h e s e a r e o s d o u t p u t p i n s ( d i g i t a l o u t p u t ) . o s d o u t p u to u t p u t i n p u t / o u t p u t M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 10 rev. 1.0 2. operation of functional bloks this microcomputer accommodates certain units in a single chip. these units include rom and ram to store instructions and data and the central processing unit (cpu) to execute arithmetic/logic operations. also included are peripheral units such as timers, serial i/o, d-a converter, dmac, osd circuit, data slicer, a-d converter, and i/o ports. the following explains each unit. 2.1 memory figure 2.1.1 is a memory map. the address space extends the 1m bytes from address 00000 16 to fffff 16 . from fffff 16 down is rom. there is 192k bytes of internal rom from d0000 16 to fffff 16 . the vector table for fixed interrupts such as the reset mapped to fffdc 16 to fffff 16 . the starting ad- dress of the interrupt routine is stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. 5k bytes of internal ram is mapped to the space from 02c00 16 to 03fff 16 . in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated. the sfr area is mapped to 00000 16 to 003ff 16 . this area accommodates the control registers for periph- eral devices such as i/o ports, a-d converter, serial i/o, and timers, etc. figures 2.1.2 to 2.1.5 are location of peripheral unit control registers. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is mapped to ffe00 16 to fffdb 16 . if the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 11 rev. 1.0 figure 2.1.1 memory map 00000 16 fffff 16 013ff 16 cffff 16 internal rom area sfr area (refer to figures 2.1.2 to 2.1.5) osd ram area internal reserved area internal reserved area ffe00 16 fffdc 16 fffff 16 undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc 90000 16 osd rom area 02c00 16 03fff 16 00400 16 b0000 16 003ff 16 01400 16 02bff 16 04000 16 8ffff 16 affff 16 d0000 16 internal ram area internal reserved area M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 12 rev. 1.0 figure 2.1.2 location of peripheral unit control registers (1) 0 0 4 0 1 6 0 0 4 1 1 6 0 0 4 2 1 6 0 0 4 3 1 6 0 0 4 4 1 6 0 0 4 5 1 6 0 0 4 6 1 6 0 0 4 7 1 6 0 0 4 8 1 6 0 0 4 9 1 6 0 0 4 a 1 6 0 0 4 b 1 6 0 0 4 c 1 6 0 0 4 d 1 6 0 0 4 e 1 6 0 0 4 f 1 6 0 0 5 0 1 6 0 0 5 1 1 6 0 0 5 2 1 6 0 0 5 3 1 6 0 0 5 4 1 6 0 0 5 5 1 6 0 0 5 6 1 6 0 0 5 7 1 6 0 0 5 8 1 6 0 0 5 9 1 6 0 0 5 a 1 6 0 0 5 b 1 6 0 0 5 c 1 6 0 0 5 d 1 6 0 0 5 e 1 6 0 0 5 f 1 6 0 0 6 0 1 6 0 1 f f 1 6 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 2 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0 0 0 9 1 6 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0 0 1 3 1 6 0 0 1 4 1 6 0 0 1 5 1 6 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 0 0 1 d 1 6 0 0 1 e 1 6 0 0 1 f 1 6 0 0 2 0 1 6 0 0 2 1 1 6 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0 0 2 5 1 6 0 0 2 6 1 6 0 0 2 7 1 6 0 0 2 8 1 6 0 0 2 9 1 6 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 0 0 2 d 1 6 0 0 2 e 1 6 0 0 2 f 1 6 0 0 3 0 1 6 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0 0 3 4 1 6 0 0 3 5 1 6 0 0 3 6 1 6 0 0 3 7 1 6 0 0 3 8 1 6 0 0 3 9 1 6 0 0 3 a 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 d m a 0 c o n t r o l r e g i s t e r ( d m 0 c o n ) d m a 0 s o u r c e p o i n t e r ( s a r 0 ) d m a 0 t r a n s f e r c o u n t e r ( t c r 0 ) d m a 1 s o u r c e p o i n t e r ( s a r 1 ) w a t c h d o g t i m e r s t a r t r e g i s t e r ( w d t s ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d c ) p r o c e s s o r m o d e r e g i s t e r 0 ( p m 0 ) a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0 ( r m a d 0 ) a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1 ( r m a d 1 ) s y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( c m 0 ) s y s t e m c l o c k c o n t r o l r e g i s t e r 1 ( c m 1 ) a d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e r ( a i e r ) p r o t e c t r e g i s t e r ( p r c r ) p r o c e s s o r m o d e r e g i s t e r 1 ( p m 1 ) d m a 0 d e s t i n a t i o n p o i n t e r ( d a r 0 ) d m a 1 c o n t r o l r e g i s t e r ( d m 1 c o n ) d m a 1 t r a n s f e r c o u n t e r ( t c r 1 ) d m a 1 d e s t i n a t i o n p o i n t e r ( d a r 1 ) t i m e r a 1 i n t e r r u p t c o n t r o l r e g i s t e r ( t a 1 i c ) u a r t 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r ( s 0 t i c ) t i m e r a 0 i n t e r r u p t c o n t r o l r e g i s t e r ( t a 0 i c ) t i m e r a 2 i n t e r r u p t c o n t r o l r e g i s t e r ( t a 2 i c ) u a r t 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r ( s 0 r i c ) d a t a s l i c e r i n t e r r u p t c o n t r o l r e g i s t e r ( d s i c ) v s y n c i n t e r r u p t c o n t r o l r e g i s t e r ( v s y n c i c ) d m a 1 i n t e r r u p t c o n t r o l r e g i s t e r ( d m 1 i c ) d m a 0 i n t e r r u p t c o n t r o l r e g i s t e r ( d m 0 i c ) m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 0 i n t e r r u p t c o n t r o l r e g i s t e r ( i i c 0 i c ) a - d c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e r ( a d i c ) b u s c o l l i s i o n d e t e c t i o n i n t e r r u p t c o n t r o l r e g i s t e r ( b c n i c ) u a r t 2 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r ( s 2 t i c ) u a r t 2 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r ( s 2 r i c ) i n t 1 i n t e r r u p t c o n t r o l r e g i s t e r ( i n t 1 i c ) t i m e r b 0 i n t e r r u p t c o n t r o l r e g i s t e r ( t b 0 i c ) t i m e r b 2 i n t e r r u p t c o n t r o l r e g i s t e r ( t b 2 i c ) t i m e r a 3 i n t e r r u p t c o n t r o l r e g i s t e r ( t a 3 i c ) i n t 0 i n t e r r u p t c o n t r o l r e g i s t e r ( i n t 0 i c ) t i m e r b 1 i n t e r r u p t c o n t r o l r e g i s t e r ( t b 1 i c ) t i m e r a 4 i n t e r r u p t c o n t r o l r e g i s t e r ( t a 4 i c ) o s d 1 i n t e r r u p t c o n t r o l r e g i s t e r ( o s d 1 i c ) o s d 2 i n t e r r u p t c o n t r o l r e g i s t e r ( o s d 2 i c ) i n t e r r u p t c o n t r o l r e s e r v e d r e g i s t e r 0 ( r e 0 i c ) i n t e r r u p t c o n t r o l r e s e r v e d r e g i s t e r 1 ( r e 1 i c ) i n t e r r u p t c o n t r o l r e s e r v e d r e g i s t e r 2 ( r e 2 i c ) i n t e r r u p t c o n t r o l r e s e r v e d r e g i s t e r 3 ( r e 3 i c ) m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 1 i n t e r r u p t c o n t r o l r e g i s t e r ( i i c 1 i c ) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 13 rev. 1.0 figure 2.1.3 location of peripheral unit control registers (2) c a p t i o n d a t a r e g i s t e r 2 ( c d 2 ) d a t a s l i c e r c o n t r o l r e g i s t e r 1 ( d s c 1 ) c o l o r p a l e t t e r e g i s t e r 1 ( c r 1 ) c o l o r p a l e t t e r e g i s t e r 2 ( c r 2 ) c o l o r p a l e t t e r e g i s t e r 3 ( c r 3 ) c o l o r p a l e t t e r e g i s t e r 4 ( c r 4 ) c o l o r p a l e t t e r e g i s t e r 5 ( c r 5 ) c o l o r p a l e t t e r e g i s t e r 6 ( c r 6 ) c o l o r p a l e t t e r e g i s t e r 7 ( c r 7 ) c o l o r p a l e t t e r e g i s t e r 9 ( c r 9 ) c o l o r p a l e t t e r e g i s t e r 1 0 ( c r 1 0 ) c o l o r p a l e t t e r e g i s t e r 1 1 ( c r 1 1 ) c o l o r p a l e t t e r e g i s t e r 1 2 ( c r 1 2 ) c o l o r p a l e t t e r e g i s t e r 1 3 ( c r 1 3 ) c o l o r p a l e t t e r e g i s t e r 1 4 ( c r 1 4 ) c o l o r p a l e t t e r e g i s t e r 1 5 ( c r 1 5 ) l e f t b o r d e r c o n t r o l r e g i s t e r ( l b r ) r i g h t b o r d e r c o n t r o l r e g i s t e r ( r b r ) s p r i t e v e r t i c a l p o s i t i o n r e g i s t e r 1 ( v s 1 ) s p r i t e h o r i z o n t a l p o s i t i o n r e g i s t e r ( h s ) d a t a s l i c e r c o n t r o l r e g i s t e r 2 ( d s c 2 ) c a p t i o n d a t a r e g i s t e r 1 ( c d 1 ) c a p t i o n p o s i t i o n r e g i s t e r ( c p s ) d a t a s l i c e r r e s e r v e d r e g i s t e r 2 ( d r 2 ) d a t a s l i c e r r e s e r v e d r e g i s t e r 1 ( d r 1 ) c l o c k r u n - i n d e t e c t r e g i s t e r ( c r d ) d a t a c l o c k p o s i t i o n r e g i s t e r ( d p s ) b l o c k c o n t r o l r e g i s t e r 1 2 ( b c 1 2) b l o c k c o n t r o l r e g i s t e r 1 3 ( b c 1 3) b l o c k c o n t r o l r e g i s t e r 1 4 ( b c 1 4) b l o c k c o n t r o l r e g i s t e r 1 5 ( b c 1 5) b l o c k c o n t r o l r e g i s t e r 1 6 ( b c 1 6) v e r t i c a l p o s i t i o n r e g i s t e r 1 ( v p 1 ) v e r t i c a l p o s i t i o n r e g i s t e r 2 ( v p 2 ) v e r t i c a l p o s i t i o n r e g i s t e r 3 ( v p 3 ) v e r t i c a l p o s i t i o n r e g i s t e r 4 ( v p 4 ) v e r t i c a l p o s i t i o n r e g i s t e r 5 ( v p 5 ) v e r t i c a l p o s i t i o n r e g i s t e r 6 ( v p 6 ) v e r t i c a l p o s i t i o n r e g i s t e r 7 ( v p 7 ) v e r t i c a l p o s i t i o n r e g i s t e r 8 ( v p 8 ) v e r t i c a l p o s i t i o n r e g i s t e r 9 ( v p 9 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 0 ( v p 1 0 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 1 ( v p 1 1 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 2 ( v p 1 2 ) o s d c o n t r o l r e g i s t e r 1 ( o c 1 ) o s d c o n t r o l r e g i s t e r 2 ( o c 2 ) h o r i z o n t a l p o s i t i o n r e g i s t e r ( h p ) c l o c k c o n t r o l r e g i s t e r ( c s ) i / o p o l a r i t y c o n t r o l r e g i s t e r ( p c ) o s d c o n t r o l r e g i s t e r 3 ( o c 3 ) r a s t e r c o l o r r e g i s t e r ( r s c ) t o p b o r d e r c o n t r o l r e g i s t e r ( t b r ) b o t t o m b o r d e r c o n t r o l r e g i s t e r ( b b r ) b l o c k c o n t r o l r e g i s t e r 1 ( b c 1) b l o c k c o n t r o l r e g i s t e r 2 ( b c 2) b l o c k c o n t r o l r e g i s t e r 3 ( b c 3) b l o c k c o n t r o l r e g i s t e r 4 ( b c 4) b l o c k c o n t r o l r e g i s t e r 5 ( b c 5) b l o c k c o n t r o l r e g i s t e r 6 ( b c 6) b l o c k c o n t r o l r e g i s t e r 7 ( b c 7) b l o c k c o n t r o l r e g i s t e r 8 ( b c 8) b l o c k c o n t r o l r e g i s t e r 9 ( b c 9) b l o c k c o n t r o l r e g i s t e r 1 0 ( b c 1 0) b l o c k c o n t r o l r e g i s t e r 1 1 ( b c 1 1) 0 2 0 0 1 6 0 2 0 1 1 6 0 2 0 2 1 6 0 2 0 3 1 6 0 2 0 4 1 6 0 2 0 5 1 6 0 2 0 6 1 6 0 2 0 7 1 6 0 2 0 8 1 6 0 2 0 9 1 6 0 2 0 a 1 6 0 2 0 b 1 6 0 2 0 c 1 6 0 2 0 d 1 6 0 2 0 e 1 6 0 2 0 f 1 6 0 2 1 0 1 6 0 2 1 1 1 6 0 2 1 2 1 6 0 2 1 3 1 6 0 2 1 4 1 6 0 2 1 5 1 6 0 2 1 6 1 6 0 2 1 7 1 6 0 2 1 8 1 6 0 2 1 9 1 6 0 2 1 a 1 6 0 2 1 b 1 6 0 2 1 c 1 6 0 2 1 d 1 6 0 2 1 e 1 6 0 2 1 f 1 6 0 2 2 0 1 6 0 2 2 1 1 6 0 2 2 2 1 6 0 2 2 3 1 6 0 2 2 4 1 6 0 2 2 5 1 6 0 2 2 6 1 6 0 2 2 7 1 6 0 2 2 8 1 6 0 2 2 9 1 6 0 2 2 a 1 6 0 2 2 b 1 6 0 2 2 c 1 6 0 2 2 d 1 6 0 2 2 e 1 6 0 2 2 f 1 6 0 2 3 0 1 6 0 2 3 1 1 6 0 2 3 2 1 6 0 2 3 3 1 6 0 2 3 4 1 6 0 2 3 5 1 6 0 2 3 6 1 6 0 2 3 7 1 6 0 2 3 8 1 6 0 2 3 9 1 6 0 2 3 a 1 6 0 2 3 b 1 6 0 2 3 c 1 6 0 2 3 d 1 6 0 2 3 e 1 6 0 2 3 f 1 6 0 2 4 0 1 6 0 2 4 1 1 6 0 2 4 2 1 6 0 2 4 3 1 6 0 2 4 4 1 6 0 2 4 5 1 6 0 2 4 6 1 6 0 2 4 7 1 6 0 2 4 8 1 6 0 2 4 9 1 6 0 2 4 a 1 6 0 2 4 b 1 6 0 2 4 c 1 6 0 2 4 d 1 6 0 2 4 e 1 6 0 2 4 f 1 6 0 2 5 0 1 6 0 2 5 1 1 6 0 2 5 2 1 6 0 2 5 3 1 6 0 2 5 4 1 6 0 2 5 5 1 6 0 2 5 6 1 6 0 2 5 7 1 6 0 2 5 8 1 6 0 2 5 9 1 6 0 2 5 a 1 6 0 2 5 b 1 6 0 2 5 c 1 6 0 2 5 d 1 6 0 2 5 e 1 6 0 2 5 f 1 6 0 2 6 0 1 6 0 2 6 1 1 6 0 2 6 2 1 6 0 2 6 3 1 6 0 2 6 4 1 6 0 2 6 5 1 6 0 2 6 6 1 6 0 2 6 7 1 6 0 2 6 8 1 6 0 2 6 9 1 6 0 2 6 a 1 6 0 2 6 b 1 6 0 2 6 f 1 6 0 2 7 0 1 6 0 2 7 1 1 6 0 2 7 2 1 6 0 2 7 3 1 6 0 2 7 4 1 6 0 2 7 5 1 6 0 2 7 6 1 6 0 2 7 7 1 6 0 2 7 8 1 6 0 2 7 9 1 6 0 2 7 a 1 6 0 2 7 b 1 6 0 2 7 c 1 6 0 2 7 d 1 6 0 2 7 e 1 6 0 2 7 f 1 6 0 2 8 0 1 6 0 2 d f 1 6 v e r t i c a l p o s i t i o n r e g i s t e r 1 3 ( v p 1 3 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 4 ( v p 1 4 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 5 ( v p 1 5 ) v e r t i c a l p o s i t i o n r e g i s t e r 1 6 ( v p 1 6 ) o s d r e s e r v e d r e g i s t e r 1 ( o r 1 ) h s y n c c o u n t e r r e g i s t e r ( h c ) h s y n c c o u n t e r l a t c h p e r i p h e r a l m o d e r e g i s t e r ( p m ) o s d r e s e r v e d r e g i s t e r 2 ( o r 2 ) o s d r e s e r v e d r e g i s t e r 3 ( o r 3 ) o s d r e s e r v e d r e g i s t e r 4 ( o r 4 ) s p r i t e o s d c o n t r o l r e g i s t e r ( s c ) s p r i t e v e r t i c a l p o s i t i o n r e g i s t e r 2 ( v s 2 ) o s d c o n t r o l r e g i s t e r 4 ( o c 4 ) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 14 rev. 1.0 figure 2.1.4 location of peripheral unit control registers (3) timer a0 register (ta0) timer a1 register (ta1) timer a2 register (ta2) timer b0 register (tb0) timer b1 register (tb1) timer b2 register (tb2) count start flag (tabsr) one-shot start flag (onsf) timer a0 mode register (ta0mr) timer a1 mode register (ta1mr) timer a2 mode register (ta2mr) timer b0 mode register (tb0mr) timer b1 mode register (tb1mr) timer b2 mode register (tb2mr) up-down flag (udf) timer a3 register (ta3) timer a4 register (ta4) timer a3 mode register (ta3mr) timer a4 mode register (ta4mr) trigger select register (trgsr) reserved register 6 (invc6) uart0 transmit/receive mode register (u0mr) uart0 transmit buffer register (u0tb) uart0 receive buffer register (u0rb) uart0 bit rate generator (u0brg) uart0 transmit/receive control register 0 (u0c0) uart0 transmit/receive control register 1 (u0c1) dma1 request cause select register (dm1sl) dma0 request cause select register (dm0sl) uart2 special mode register (u2smr) uart2 receive buffer register (u2rb) uart2 transmit buffer register (u2tb) uart2 transmit/receive control register 0 (u2c0) uart2 transmit/receive mode register (u2mr) uart2 transmit/receive control register 1 (u2c1) uart2 bit rate generator (u2brg) 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 02e0 16 02e1 16 02e2 16 02e3 16 02e4 16 02e5 16 02e6 16 02e7 16 02e8 16 02e9 16 02ea 16 02eb 16 02ec 16 02ed 16 02ee 16 02ef 16 0339 16 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 interrupt request cause select register (ifsr) reserved register 0 (invc0) uart transmit/receive control register 2 (ucon) reserved register 1 (invc1) reserved register 3 (invc3) reserved register 4 (invc4) reserved register 2 (invc2) reserved register 5 (invc5) i 2 c0 status register (iic0s1) i 2 c0 control register (iic0s1d) i 2 c0 address register (iic0s0d) i 2 c0 data shift register (iic0s0) i 2 c0 port selection register (iic0s2d) i 2 c0 transmit buffer register (iic0s0s) i 2 c0 clock control register (iic0s2) i 2 c1 status register (iic1s1) i 2 c1 control register (iic1s1d) i 2 c1 address register (iic1s0d) i 2 c1 data shift register (iic1s0) i 2 c1 port selection register (iic1s2d) i 2 c1 transmit buffer register (iic1s0s) i 2 c1 clock control register (iic1s2) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 15 rev. 1.0 figure 2.1.5 location of peripheral unit control registers (4) 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 a-d register 5 (ad5) a-d register 0 (ad0) a-d register 1 (ad1) a-d register 2 (ad2) a-d register 3 (ad3) a-d register 4 (ad4) port p0 register (p0) port p0 direction register (pd0) port reserved register 1 (pr1) port reserved register 2 (pr2) port p2 register (p2) port p2 direction register (pd2) port p3 register (p3) port p3 direction register (pd3) port p4 register (p4) port p4 direction register (pd4) port p5 register (p5) port p5 direction register (pd5) port p6 register (p6) port p6 direction register (pd6) port p7 register (p7) port p7 direction register (pd7) port p8 register (p8) port p8 direction register (pd8) port p9 register (p9) port p9 direction register (pd9) port p10 register (p10) port p10 direction register (pd10) pull-up control register 0 (pur0) pull-up control register 1 (pur1) pull-up control register 2 (pur2) a-d control register 0 (adcon0) a-d control register 1 (adcon1) d-a register 0 (da0) d-a register 1 (da1) d-a control register (dacon) a-d control register 2 (adcon2) port reserved register 3 (pr3) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 16 rev. 1.0 2.2 central processing unit (cpu) the cpu has a total of 13 registers shown in figure 2.2.1. seven of these registers (r0, r1, r2, r3, a0, a1, and fb) come in two sets; therefore, these have two register banks. figure 2.2.1 central processing unit register h l b15 b8 b7 b0 r0 (note) h l b15 b8 b7 b0 r1 (note) r2 (note) b15 b0 r3 (note) b15 b0 a0 (note) b15 b0 a1 (note) b15 b0 fb (note) b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 hl program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register pc intb usp isp sb flg note: these registers consist of two register banks. c d z s b o i u ipl M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 17 rev. 1.0 2.2.1 data registers (r0, r0h, r0l, r1, r1h, r1l, r2, and r3) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h/r1h), and low-order bits as (r0l/r1l). in some instructions, registers r2 and r0, as well as r3 and r1 can use as 32-bit data registers (r2r0/r3r1). 2.2.2 address registers (a0 and a1) address registers (a0 and a1) are configured with 16 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). 2.2.3 frame base register (fb) frame base register (fb) is configured with 16 bits, and is used for fb relative addressing. 2.2.4 program counter (pc) program counter (pc) is configured with 20 bits, indicating the address of an instruction to be executed. 2.2.5 interrupt table register (intb) interrupt table register (intb) is configured with 20 bits, indicating the start address of an interrupt vector table. 2.2.6 stack pointer (usp/isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each config- ured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). 2.2.7 static base register (sb) static base register (sb) is configured with 16 bits, and is used for sb relative addressing. 2.2.8 flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure 2.2.2 shows the flag register (flg). the following explains the function of each flag: ? bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ? bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is 1, a single-step interrupt is generated after instruction execution. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 2: zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, cleared to 0. ? bit 3: sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, cleared to 0 . ? bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 18 rev. 1.0 ? bit 5: overflow flag (o flag) this flag is set to 1 when an arithmetic operation resulted in overflow; otherwise, cleared to 0. ? bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is 0, and is enabled when this flag is 1. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 7: stack pointer select flag (u flag) interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1. this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software interrupt nos. 0 to 31 is executed. ? bits 8 to 11: reserved area ? bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. ? bit 15: reserved area the c, z, s, and o flags are changed when instructions are executed. see the software manual for details. figure 2.2.2 flag register (flg) carry flag debug flag zero flag sign flag register bank select fla g overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt prio r reserved area flag register (flg) c d z s b o i u ipl b0 b15 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 19 rev. 1.0 2.3 reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see software reset for details of software resets.) this section explains on hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level l (0.2v cc max.) for at least 20 cycles. when the reset pin level is then returned to the h level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. figure 2.3.1 shows the example reset circuit. figure 2.3.2 shows the reset sequence. figure 2.3.1 example reset circuit reset v cc 0.9v reset v cc 0v 0v 5v 5v 4.5v example when f(x in ) = 10 mhz and v cc = 5v. 2.3.1 software reset writing 1 to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software) reset to the microcomputer. a software reset has almost the same effect as a hardware reset. the contents of internal ram are preserved. figure 2.3.2 reset sequence bclk address content of reset vector single-chip mode bclk 24cycles content of reset vector ffffe 16 x in reset ffffc 16 more than 20 cycles are needed M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 20 rev. 1.0 ____________ 2.3.2 pin status when reset pin level is l ____________ table 2.3.1 shows the statuses of the other pins while the reset pin level is l. figures 2.3.3 and 2.3.4 show the internal status of the microcomputer immediately after the reset is cancelled. ____________ table 2.3.1 pin status when reset pin level is l status cnv ss = v ss pin name input port (floating) r, g, b, out1,out2 output port cv in , v hold , hlf osc1 input/output port osc2 input port output port p0, p2 , p3, p4 0 to p4 3 , p5 0 , p5 2 , p5 3 , p5 5 , p6 2 , p6 3 , p6 7 , p7 0 to p7 2 , p7 4 , p7 6 , p8 2 , p9 0 , p9 3 , p9 4 , p10 0 , p10 1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 21 rev. 1.0 figure 2.3.3 devices internal status after a reset is cleared (1) x : n o t h i n g i s m a p p e d t o t h i s b i t ? : u n d e f i n e d t h e c o n t e n t o f o t h e r r e g i s t e r s a n d r a m i s u n d e f i n e d w h e n t h e m i c r o c o m p u t e r i s r e s e t . t h e i n i t i a l v a l u e s m u s t t h e r e f o r e b e s e t . t i m e r b 0 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r b 1 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r b 2 i n t e r r u p t c o n t r o l r e g i s t e r i n t 0 i n t e r r u p t c o n t r o l r e g i s t e r i n t 1 i n t e r r u p t c o n t r o l r e g i s t e r ( 0 0 5 a 1 6 ) ( 0 0 5 b 1 6 ) ? 0 0 0 ? 0 0 0 ( 0 0 5 c 1 6 ) ? 0 0 0 ( 0 0 5 d 1 6 ) ? 000 00 ( 0 0 5 e 1 6 ) ? 000 00 c l o c k c o n t r o l r e g i s t e r i / o p o l a r i t y c o n t r o l r e g i s t e r h o r i z o n t a l p o s i t i o n r e g i s t e r o s d c o n t r o l r e g i s t e r 1 o s d c o n t r o l r e g i s t e r 3 o s d c o n t r o l r e g i s t e r 2 r a s t e r c o l o r r e g i s t e r ( 0 2 0 5 1 6 ) 0 0 1 6 ( 0 2 0 6 1 6 ) 0 0 1 6 ( 0 2 0 3 1 6 ) 0 0 1 6 ( 0 2 0 4 1 6 ) 0 0 1 6 ( 0 2 0 2 1 6 ) 0 0 1 6 ( 0 2 0 7 1 6 ) ( 0 2 0 8 1 6 ) 0 0 1 6 s p r i t e h o r i z o n t a l p o s i t i o n r e g i s t e r ( h i g h - o r d e r ) l e f t b o r d e r c o n t r o l r e g i s t e r r i g h t b o r d e r c o n t r o l r e g i s t e r ( 0 2 7 9 1 6 ) ( 0 2 7 0 1 6 ) ( 0 2 7 2 1 6 ) ( 0 2 7 3 1 6 ) 0 0 1 6 0 1 1 6 ( 0 2 7 1 1 6 ) 0 00 0 00 0 00 s p r i t e o s d c o n t r o l r e g i s t e r ( 0 2 0 1 1 6 ) 0 00 0 0 00 00 0 0 10 ( 0 0 0 4 1 6 ) p r o c e s s o r m o d e r e g i s t e r 0 ( n o t e ) 0 0 1 6 ( 0 0 0 5 1 6 ) p r o c e s s o r m o d e r e g i s t e r 1 0 0 0 ( 0 0 0 6 1 6 ) s y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( 0 0 0 7 1 6 ) s y s t e m c l o c k c o n t r o l r e g i s t e r 1 ( 0 0 0 9 1 6 ) a d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e r 0 0 p r o t e c t r e g i s t e r( 0 0 0 a 1 6 ) 00 0 ( 0 0 0 f 1 6 ) w a t c h d o g t i m e r c o n t r o l r e g i s t e r 0 0? 0???? ( 0 0 1 4 1 6 ) a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1 ( 0 0 1 5 1 6 ) ( 0 0 1 6 1 6 ) 0 0 0 1 6 0 0 1 6 0 0 0 ( 0 0 2 c 1 6 ) d m a 0 c o n t r o l r e g i s t e r 00000?00 ( 0 0 3 c 1 6 ) d m a 1 c o n t r o l r e g i s t e r 00000?00 ( 0 0 1 0 1 6 ) a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0 ( 0 0 1 1 1 6 ) ( 0 0 1 2 1 6 ) 0 0 0 1 6 0 0 1 6 0 0 0 ( 0 0 4 4 1 6 ) o s d 1 i n t e r r u p t c o n t r o l r e g i s t e r ?000 ( 0 0 4 8 1 6 ) o s d 2 i n t e r r u p t c o n t r o l r e g i s t e r ?000 4 8 1 6 2 0 1 6 0 0 0 ( 0 0 4 b 1 6 ) d m a 0 i n t e r r u p t c o n t r o l r e g i s t e r ? 0 0 0 ( 0 0 4 c 1 6 ) d m a 1 i n t e r r u p t c o n t r o l r e g i s t e r ? 0 0 0 ( 0 0 4 a 1 6 ) b u s c o l l i s i o n d e t e c t i o n i n t e r r u p t c o n t r o l r e g i s t e r 0 0 0 ? u a r t 2 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r u a r t 2 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r u a r t 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r u a r t 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r d a t a s l i c e r i n t e r r u p t c o n t r o l r e g i s t e r v s y n c i n t e r r u p t c o n t r o l r e g i s t e r ( 0 0 4 f 1 6 ) ( 0 0 5 0 1 6 ) ( 0 0 5 1 1 6 ) ( 0 0 5 2 1 6 ) ( 0 0 5 3 1 6 ) ( 0 0 5 4 1 6 ) ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 t i m e r a 0 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r a 1 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r a 2 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r a 3 i n t e r r u p t c o n t r o l r e g i s t e r t i m e r a 4 i n t e r r u p t c o n t r o l r e g i s t e r ( 0 0 5 5 1 6 ) ( 0 0 5 6 1 6 ) ( 0 0 5 7 1 6 ) ( 0 0 5 8 1 6 ) ( 0 0 5 9 1 6 ) ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 a - d c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e r ( 0 0 4 e 1 6 ) ? 0 0 0 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 0 i n t e r r u p t c o n t r o l r e g i s t e r ( 0 0 4 d 1 6 ) ? 0 0 0 0 ( 0 2 0 9 1 6 ) 0 0 1 6 ( 0 0 4 9 1 6 ) m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 1 i n t e r r u p t c o n t r o l r e g i s t e r ?000 00 o s d r e s e r v e d r e g i s t e r 3 h s y n c c o u n t e r r e g i s t e r p e r i p h e r a l m o d e r e g i s t e r ( 0 2 7 b 1 6 ) ( 0 2 7 e 1 6 ) ( 0 2 7 d 1 6 ) 0 00 00 00000 0 0 1 6 o s d r e s e r v e d r e g i s t e r 4 ( 0 2 7 a 1 6 ) 00 00 0 00 o s d r e s e r v e d r e g i s t e r 2 ( 0 2 7 c 1 6 ) 0 0 1 6 d a t a s l i c e r c o n t r o l r e g i s t e r 1 d a t a s l i c e r c o n t r o l r e g i s t e r 2 c a p t i o n p o s i t i o n r e g i s t e r o s d c o n t r o l r e g i s t e r 4 ( 0 2 6 0 1 6 ) 0 0 1 6 ( 0 2 6 1 1 6 ) 0 00 ( 0 2 6 6 1 6 ) ? ???? 0 00 ? 0000 ( 0 2 5 f 1 6 ) 0 0 o s d r e s e r v e d r e g i s t e r 1( 0 2 5 d 1 6 ) 0 0 1 6 c l o c k r u n - i n d e t e c t r e g i s t e r d a t a c l o c k p o s i t i o n r e g i s t e r ( 0 2 6 9 1 6 ) 0 0 1 6 ( 0 2 6 a 1 6 ) 00 01 0 d a t a s l i c e r r e s e r v e d r e g i s t e r 2( 0 2 6 7 1 6 ) 0 0 1 6 d a t a s l i c e r r e s e r v e d r e g i s t e r 1( 0 2 6 8 1 6 ) 0 0 1 6 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 22 rev. 1.0 figure 2.3.4 devices internal status after a reset is cleared (2) x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. port reserved register 2 port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register port p9 direction register port p10 direction register pull-up control register 0 pull-up control register 1(note) pull-up control register 2 data registers (r0/r1/r2/r3) frame base register (fb) address registers (a0/a1) interrupt table register (intb) user stack pointer (usp) interrupt stack pointer (isp) static base register (sb) flag register (flg) 0000 16 0000 16 0000 16 00000 16 0000 16 0000 16 0000 16 0000 16 port reserved register 3 (03e3 16 ) (03e6 16 ) (03e7 16 ) (03ea 16 ) (03eb 16 ) (03ee 16 ) (03ef 16 ) (03f2 16 ) (03f3 16 ) (03f6 16 ) (03fc 16 ) (03fd 16 ) (03fe 16 ) 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 0 0 000 (03ff 16 ) 00 16 (0377 16 ) 00 16 uart2 special mode register (0383 16 ) trigger select register (0384 16 ) up-down flag (0396 16 ) timer a0 mode register (0397 16 ) timer a1 mode register (0398 16 ) timer a2 mode register (039b 16 ) timer b0 mode register (039c 16 ) timer b1 mode register (039d 16 ) timer b2 mode register (0399 16 ) timer a3 mode register (039a 16 ) timer a4 mode register (0382 16 ) one-shot start flag 00 16 00 16 0 00 16 00 16 00 16 00 16 00 16 0? 0000 00? 0000 00? 0000 (03a0 16 ) uart0 transmit/receive mode register (03a4 16 ) uart0 transmit/receive control register 0 (03a5 16 ) uart0 transmit/receive control register 1 00 16 0 00 0 000 uart2 transmit/receive control register 1 uart2 transmit/receive control register 0 count start flag (037d 16 ) (037c 16 ) (0380 16 ) 00 16 0 (0381 16 ) reserved register 6 02 16 08 16 08 16 02 16 (0378 16 ) 00 16 uart2 transmit/receive mode register (03a8 16 ) 00 16 reserved register 2 port p0 direction register d-a control register a-d control register 0 a-d control register 1 (03e2 16 ) 00 16 (03dc 16 ) 00 16 (03d6 16 ) (03d7 16 ) 000 0??? 0 00 16 (03b8 16 ) dma0 request cause select register (03ba 16 ) dma1 request cause select register 00 16 00 16 (03d4 16 ) a-d control register 2 0 ? ? ? (03b0 16 ) uart transmit/receive control register 2 0 0 0 0 0 0 0 0 0 0 0 (0348 16 ) 00 16 reserved register 0 (035f 16 ) 00 16 interrupt request cause select register (0340 16 ) reserved register 1 (0366 16 ) 40 16 reserved register 4 (0362 16 ) 40 16 reserved register 3 ? ? ? 0 0 0 ?? (0376 16 ) 00 16 reserved register 5 (02ea 16 ) i 2 c1 status register (02eb 16 ) 00 16 i 2 c1 control register (02ed 16 ) i 2 c1 port selection register (02ec 16 ) 00 16 i 2 c1 clock control register (02e9 16 ) i 2 c1 address register 00 16 (02e2 16 ) i 2 c0 status register (02e3 16 ) 00 16 i 2 c0 control register (02e5 16 ) i 2 c0 port selection register (02e4 16 ) 00 16 i 2 c0 clock control register 0 0 0 0 0 0 1? (02e1 16 ) i 2 c0 address register 00 16 0 0 0 0 0 0 1? 0 0 0 ? 0 0 ?0 0 0 0 ? 0 0 ?0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 23 rev. 1.0 2.4 single-chip mode this microcomputer supports single-chip mode only. in single-chip mode, only internal memory space (sfr, osd ram, internal ram, and internal rom) can be accessed. ports p0, p2 to p10 can be used as programmable i/o ports or as i/o ports for the internal peripheral functions. figure 2.4.1 shows the processor mode register 0 and figure 2.4.2 shows the processor mode register 1. figure 2.4.3 shows the memory map. figure 2.4.1 processor mode register 0 p r o c e s s o r m o d e r e g i s t e r 0 ( n o t e ) s y m b o la d d r e s sw h e n r e s e t p m 00 0 0 4 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : i n h i b i t e d 1 0 : i n h i b i t e d 1 1 : i n h i b i t e d b 1 b 0 p m 0 3 p m 0 1 p m 0 0 p r o c e s s o r m o d e b i t s o f t w a r e r e s e t b i t t h e d e v i c e i s r e s e t w h e n t h i s b i t i s s e t t o 1 . t h e v a l u e o f t h i s b i t i s 0 w h e n r e a d . n o t e : s e t b i t 1 o f t h e p r o t e c t r e g i s t e r ( a d d r e s s 0 0 0 a 1 6 ) t o 1 w h e n w r i t i n g n e w v a l u e s t o t h i s r e g i s t e r . r e s e r v e d b i t m u s t a l w a y s b e s e t t o 0 r e s e r v e d b i t s m u s t a l w a y s b e s e t t o 0 0000 0 00 figure 2.4.2 processor mode register 1 p r o c e s s o r m o d e r e g i s t e r 1 ( n o t e 1 ) s y m b o la d d r e s sw h e n r e s e t p m 10 0 0 5 1 6 0 0 0 0 0 x 0 0 2 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . r e s e r v e d b i t m u s t a l w a y s b e s e t t o 0 0 n o t e s 1 : s e t b i t 1 o f t h e p r o t e c t r e g i s t e r ( a d d r e s s 0 0 0 a 1 6 ) t o 1 w h e n w r i t i n g n e w v a l u e s t o t h i s r e g i s t e r . 2: a s t h i s b i t b e c o m e s 0 a t r e s e t , m u s t a l w a y s b e s e t t o 1 a f t e r r e s e t r e l e a s e . p m 1 7 w a i t b i t 0 : n o w a i t s t a t e 1 : w a i t s t a t e i n s e r t e d r e s e r v e d b i t s m u s t a l w a y s b e s e t t o 0 000 0 r e s e r v e d b i t ( n o t e 2 ) m u s t a l w a y s b e s e t t o 1 1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 24 rev. 1.0 figure 2.4.3 memory map in single-chip mode sfr area osd ram internal ram area 00000 16 00400 16 013ff 16 02c00 16 03fff 16 internal reserved area 90000 16 osd rom affff 16 cffff 16 internal rom area fffff 16 003ff 16 01400 16 02bff 16 04000 16 8ffff 16 b0000 16 internal reserved area d0000 16 internal reserved area M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 25 rev. 1.0 2.4.1 software wait a software wait can be inserted by setting the wait bit (bit 7) of processor mode register 1 (address 0005 16 ). a software wait is inserted in the internal rom/ram area by setting the wait bit of the processor mode register 1. when set to 0, each bus cycle is executed in one bclk cycle. when set to 1, each bus cycle is executed in two bclk cycles. after the microcomputer has been reset, this bit defaults to 0. the sfr area and the osd ram area is always accessed in two bclk cycles regardless of the setting of these control bits. table 2.4.1 shows the software wait and bus cycles. figure 2.4.4 shows example bus timing when using software waits. table 2.4.1 software waits and bus cycles area wait bit bus cycle 1 2 bclk cycles sfr/ osd ram internal rom/ram 0 1 bclk cycle invalid 2 bclk cycles M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 26 rev. 1.0 figure 2.4.4 typical bus timings using software wait output input address address bus cycle < with wait > bclk read signal write signal data bus address bus chip select bclk read signal write signal address bus address address bus cycle < no wait > output data bus chip select input M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 27 rev. 1.0 table 2.5.1. clock oscillation circuits main clock oscillation circuit osd oscillation circuit use of clock ? cpus operating clock source ? osds operating clock source ? internal peripheral units operating clock source usable oscillator ? ceramic resonator ? ceramic resonator (or quartz-crystal oscillator) (or quartz-crystal oscillator) ? lc oscillator pins to connect oscillator x in , x out osc1, osc2 oscillation stop/restart function available oscillator status immediately after reset oscillating other externally derived clock can be input 2.5.1 example of oscillator circuit figure 2.5.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figure 2.5.1 vary with each oscillator used. use the values recommended by the manufacturer of your oscillator. m i c r o c o m p u t e r ( b u i l t - i n f e e d b a c k r e s i s t o r ) x i n x o u t e x t e r n a l l y d e r i v e d c l o c k o p e n v c c v s s m i c r o c o m p u t e r ( b u i l t - i n f e e d b a c k r e s i s t o r ) x i n x o u t r d c i n c o u t ( n o t e ) n o t e : i n s e r t a d a m p i n g r e s i s t o r i f r e q u i r e d . t h e r e s i s t a n c e w i l l v a r y d e p e n d i n g o n t h e o s c i l l a t o r a n d t h e o s c i l l a t i o n d r i v e c a p a c i t y s e t t i n g . u s e t h e v a l u e r e c o m m e n d e d b y t h e m a k e r o f t h e o s c i l l a t o r . w h e n t h e o s c i l l a t i o n d r i v e c a p a c i t y i s s e t t o l o w , c h e c k t h a t o s c i l l a t i o n i s s t a b l e . w h e n b e i n g s p e c i f i e d t o c o n n e c t a f e e d b a c k r e s i s t o r e x t e r n a l l y b y t h e m a n u f a c t u r e , c o n n e c t a f e e d b a c k r e s i s t o r b e t w e e n p i n s x i n a n d x o u t . figure 2.5.1 examples of main clock 2.5 clock generating circuit the clock generating circuit contains each oscillator circuit that supplies the operating clock sources to the cpu and internal peripheral units and that supplies the operating clock source to osd. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 28 rev. 1.0 2.5.2 osd oscillation circuit the osd clock oscillation circuit can obtain simply a clock for osd by connecting an lc oscillator or a ceramic resonator (or a quartz-crystal oscillator) across the pins osc1 and osc2. which of lc oscillator or a ceramic resonator (or a quartz-crystal oscillator) is selected by setting bits 1 and 2 of the clock control register (address 0205 16 ). figure 2.5.2 osd clock connection example 2.5.3 clock control figure 2.5.3 shows the block diagram of the main clock generating circuit. sub clock cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 wdci : bit i at address 000f 16 cm10 ?? write signal q s r wait instruction x out main clock cm02 f 1 q s r interrupt request level judgment output reset software reset f ad divider a d 1/2 1/2 1/2 1/2 cm06=0 cm17,cm16=00 cm06=0 cm17,cm16=01 cm06=0 cm17,cm16=10 cm06=1 cm06=0 cm17,cm16=11 d a details of divider x in f 8 f 32 c b b 1/2 c f 32 sio2 f 8 sio2 f 1 sio2 bclk figure 2.5.3 clock generating circuit osc2 osc1 l c1 c2 microcomputer M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 29 rev. 1.0 the following paragraphs describes the clocks generated by the clock generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after a reset, the clock is divided by 8 to the bclk. the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the x in -x out drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the main clock oscillation circuit reduces the power dissipa- tion. this bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode and at a reset. (2) bclk the internal clock f is the clock that drives the cpu, and is the clock derived by dividing the main clock by 1, 2, 4, 8, or 16. the bclk is derived by dividing the main clock by 8 after a reset. the main clock division select bit 0 (bit 6 at address 0006 16 ) changes to 1 when shifting from high- speed/medium-speed to stop mode and at reset. (3) peripheral function clock ( f 1, f 8, f 32, f 1sio2 , f 8sio2 , f 32sio2, f ad ) the clock for the peripheral devices is derived by dividing the main clock by 1, 8 or 32. the peripheral function clock is stopped by stopping the main clock or by setting the wait peripheral function clock stop bit (bit 2 at 0006 16 ) to 1 and then executing a wait instruction. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 30 rev. 1.0 figures 2.5.4 and 2.5.5 shows the system clock control registers 0 and 1. figure 2.5.5 system clock control register 1 figures 2.5.4 system clock control register 0 s y s t e m c l o c k c o n t r o l r e g i s t e r 1 ( n o t e 1 ) s y m b o la d d r e s sw h e n r e s e t c m 10 0 0 7 1 6 2 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 c m 1 0 a l l c l o c k s t o p c o n t r o l b i t ( n o t e 4 ) 0 : c l o c k o n 1 : a l l c l o c k s o f f ( s t o p m o d e ) n o t e s 1 : s e t b i t 0 o f t h e p r o t e c t r e g i s t e r ( a d d r e s s 0 0 0 a 1 6 ) t o 1 b e f o r e w r i t i n g t o t h i s r e g i s t e r . 2 : t h i s b i t c h a n g e s t o 1 w h e n s h i f t i n g f r o m h i g h - s p e e d / m e d i u m - s p e e d m o d e t o s t o p m o d e a n d a t a r e s e t . 3 : c a n b e s e l e c t e d w h e n b i t 6 o f t h e s y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( a d d r e s s 0 0 0 6 1 6 ) i s 0 . i f 1 , d i v i s i o n m o d e i s f i x e d a t 8 . 4 : i f t h i s b i t i s s e t t o 1 , x o u t t u r n s h , a n d t h e b u i l t - i n f e e d b a c k r e s i s t o r i s c u t o f f . c m 1 5 x i n - x o u t d r i v e c a p a c i t y s e l e c t b i t ( n o t e 2 ) 0 : l o w 1 : h i g h w r c m 1 6 c m 1 7 m a i n c l o c k d i v i s i o n s e l e c t b i t 1 ( n o t e 3 ) 0 0 : n o d i v i s i o n m o d e 0 1 : d i v i s i o n b y 2 m o d e 1 0 : d i v i s i o n b y 4 m o d e 1 1 : d i v i s i o n b y 1 6 m o d e b 7 b 6 0 0 r e s e r v e d b i t s m u s t a l w a y s b e s e t t o 0 0 0 s y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( n o t e 1 ) s y m b o la d d r e s sw h e n r e s e t c m 00 0 0 6 1 6 4 8 1 6 b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 c m 0 2 r e s e r v e d b i t s c m 0 6 w a i t p e r i p h e r a l f u n c t i o n c l o c k s t o p b i t 0 : d o n o t s t o p p e r i p h e r a l f u n c t i o n c l o c k i n w a i t m o d e 1 : s t o p p e r i p h e r a l f u n c t i o n c l o c k i n w a i t m o d e m a i n c l o c k d i v i s i o n s e l e c t b i t 0 ( n o t e 2 ) 0 : c m 1 6 a n d c m 1 7 v a l i d 1 : d i v i s i o n b y 8 m o d e n o t e s 1 : s e t b i t 0 o f t h e p r o t e c t r e g i s t e r ( a d d r e s s 0 0 0 a 1 6 ) t o 1 b e f o r e w r i t i n g t o t h i s r e g i s t e r . 2 : t h i s b i t c h a n g e s t o 1 w h e n s h i f t i n g f r o m h i g h - s p e e d / m e d i u m - s p e e d m o d e t o s t o p m o d e a n d a t a r e s e t . w r 00100 m u s t a l w a y s b e s e t t o 0 r e s e r v e d b i t m u s t a l w a y s b e s e t t o 1 r e s e r v e d b i t s m u s t a l w a y s b e s e t t o 0 r e s e r v e d b i t m u s t a l w a y s b e s e t t o 0 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 31 rev. 1.0 2.5.5 wait mode when a wait instruction is executed, the bclk stops and the microcomputer enters the wait mode. in this mode, oscillation continues but the bclk and watchdog timer stop. writing 1 to the wait peripheral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. table 2.5.3 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or an interrupt. if an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as bclk, the clock that had been selected when the wait instruction was executed. table 2.5.2 port status during stop mode pin state port retains status before stop mode 2.5.4 stop mode writing 1 to the all-clock stop control bit (bit 0 at address 0007 16 ) stops all oscillation and the microcom- puter enters stop mode. in stop mode, the content of the internal ram is retained provided that v cc remains above 4.5v. because the oscillation, bclk, f 1 to f 32 , f 1sio2 to f 32sio2 , and f ad stops in stop mode, peripheral functions such as the a-d converter and watchdog timer do not function. however, timer b operates provided that the event counter mode is set to an external pulse, and uarti (i = 0, 2) functions provided an external clock is selected. table 2.5.2 shows the status of the ports in stop mode. stop mode is cancelled by a hardware reset or an interrupt. if an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. if returning by an interrupt, that interrupt routine is executed. when shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 0006 16 ) is set to 1. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. table 2.5.3 port status during wait mode pin state port retains status before wait mode M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 32 rev. 1.0 0 1 0 invalid division by 2 mode 1 0 0 invalid division by 4 mode invalid invalid 1 invalid division by 8 mode 1 1 0 invalid division by 16 mode 0 0 0 invalid no-division mode 2.5.6 status transition of bclk power dissipation can be reduced and low-voltage operation achieved by changing the count source for bclk. table 2.5.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. after a reset, operation defaults to division by 8 mode. when shifting to stop mode, the main clock division select bit 0 (bit 6 at address 0006 16 ) is set to 1. the following shows the operational modes of internal clock f . (1) division by 2 mode the main clock is divided by 2 to obtain the bclk. (2) division by 4 mode the main clock is divided by 4 to obtain the bclk. (3) division by 8 mode the main clock is divided by 8 to obtain the bclk. note that oscillation of the main clock must have stabilized before transferring from this mode to another mode. (4) division by 16 mode the main clock is divided by 16 to obtain the bclk. (5) no-division mode the main clock is used as the bclk. cm17 cm16 cm06 cm04 operating mode of bclk table 2.5.4 operating modes dictated by settings of system clock control registers 0 and 1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 33 rev. 1.0 2.5.7 power control the following is a description of the three available power control modes: modes power control is available in three modes. (1) normal operation mode n high-speed mode divide-by-1 frequency of the main clock becomes the bclk. the cpu operates with the internal clock selected. each peripheral function operates according to its assigned clock. n medium-speed mode divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the bclk. the cpu operates according to the internal clock selected. each peripheral function operates according to its assigned clock. (2) wait mode the cpu operation is stopped. the oscillators do not stop. (3) stop mode all oscillators stop. the cpu and all built-in peripheral functions stop. this mode, among the three modes listed here, is the most effective in decreasing power consumption. figure 2.5.6 is the state transition diagram of the above modes. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 34 rev. 1.0 figure 2.5.6 state transition diagram of power control mode m a i n c l o c k i s o s c i l l a t i n g b c l k : f ( x i n ) / 1 6 c m 0 6 = 0 c m 1 7 = 1 c m 1 6 = 1 b c l k : f ( x i n ) / 4 c m 0 6 = 0 c m 1 7 = 1 c m 1 6 = 0 b c l k : f ( x i n ) c m 0 6 = 0 c m 1 7 = 0 c m 1 6 = 0 b c l k : f ( x i n ) / 2 c m 0 6 = 0 c m 1 7 = 0 c m 1 6 = 1 h i g h - s p e e d m o d em e d i u m - s p e e d m o d e ( d i v i d e d - b y - 2 ) m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 1 6 ) m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 4 ) r e s e t m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 8 m o d e ) i n t e r r u p t t r a n s i t i o n o f s t o p m o d e , w a i t m o d e t r a n s i t i o n o f n o r m a l m o d e n o t e s 1 : s w i t c h c l o c k s a f t e r o s c i l l a t i o n o f m a i n c l o c k i s s u f f i c i e n t l y s t a b l e . 2: c h a n g e c m 0 6 a f t e r c h a n g i n g c m 1 7 a n d c m 1 6 . 3: t r a n s i t i n a c c o r d a n c e w i t h a r r o w s . h i g h - s p e e d / m e d i u m - s p e e d m o d e w a i t m o d e w a i t i n s t r u c t i o n i n t e r r u p t c p u o p e r a t i o n s t o p p e d s t o p m o d e c m 1 0 = 1 a l l o s c i l l a t o r s s t o p p e d m a i n c l o c k i s o s c i l l a t i n g m e d i u m - s p e e d m o d e ( d i v i d e d - b y - 8 m o d e ) b c l k : f ( x i n ) / 8 c m 0 6 = 1 c m 0 6 = 1 s t o p m o d e c m 1 0 = 1 a l l o s c i l l a t o r s s t o p p e d i n t e r r u p t w a i t m o d e w a i t i n s t r u c t i o n i n t e r r u p t c p u o p e r a t i o n s t o p p e d ( s e e t h e f i g u r e b e l o w a s f o r t r a n s i t i o n o f n o r m a l m o d e ) c m 0 6 = 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 35 rev. 1.0 2.6 protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure 2.6.1 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control reg- ister 0 (address 0006 16 ), system clock control register 1 (address 0007 16 ) and port p9 direction register (address 03f3 16 ) can only be changed when the respective bit in the protect register is set to 1. there- fore, important outputs can be allocated to port p9. if, after 1 (write-enabled) has been written to the port p9 direction register write-enable bit (bit 2 at address 000a 16 ), a value is written to any address, the bit automatically reverts to 0 (write-inhibited). however, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000a 16 ) and processor mode register 0 and 1 write-enable bit (bit 1 at 000a 16 ) do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0. protect register symbol address when reset prcr 000a 16 xxxxx000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write-inhibited 1 : write-enabled prc1 prc0 prc2 enables writing to processor mode registers 0 and 1 (addresses 0004 16 and 0005 16 ) function 0 : write-inhibited 1 : write-enabled enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) enables writing to port p9 direction register (address 03f3 16 ) (note ) 0 : write-inhibited 1 : write-enabled w r nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. note: writing a value to an address after 1 is written to this bit returns the bit to 0. other bits do not automatically return to 0 and they must therefore be reset b y the pro g ram. figure 2.6.1 protect register M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 36 rev. 1.0 2.7 interrupts 2.7.1 type of interrupts figure 2.7.1 lists the types of interrupts. figure 2.7.1 classification of interrupts interrupt ? ? ? y ? ? ? t software hardware ? y ? t special peripheral i/o (note) ? y ? t undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? y ? ? t reset ________ dbc watchdog timer single step address matched note: peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system. ? maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 37 rev. 1.0 2.7.2 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. ? undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. ? overflow interrupt an overflow interrupt occurs when executing the into instruction with the overflow flag (o flag) set to 1. the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub ? brk interrupt a brk interrupt occurs when executing the brk instruction. ? int interrupt an int interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing the int instruction. software interrupt numbers 0 through 31 are assigned to peripheral i/o interrupts, so executing the int instruction allows executing the same interrupt routine that a peripheral i/o interrupt does. the stack pointer (sp) used for the int interrupt is dependent on which software interrupt number is involved. so far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (u flag) when it accepts an interrupt request. if change the u flag to 0 and select the interrupt stack pointer (isp), and then execute an interrupt sequence. when returning from the interrupt routine, the u flag is returned to the state it was before the acceptance of interrupt re- quest. so far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 38 rev. 1.0 2.7.3 hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are non-maskable interrupts. ? reset ____________ reset occurs if an l is input to the reset pin. ________ ? dbc interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. ? watchdog timer interrupt generated by the watchdog timer. ? single-step interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. with the debug flag (d flag) set to 1, a single-step interrupt occurs after one instruction is executed. ? address match interrupt an address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1. if an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. for address match interrupt, see 2.11 address match interrupt. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. the interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the ini instruction uses. peripheral i/o interrupts are maskable interrupts. ? bus collision detection interrupt this is an interrupt that the serial i/o bus collision detection generates. ? dma0 interrupt, dma1 interrupt these are interrupts dma generates. ? v sync interrupt v sync interrupt occurs if a v sync edge is input. ? a-d conversion interrupt this is an interrupt that the a-d converter generates. ? uart0 transmission, uart2 transmission interrupts these are interrupts that the serial i/o transmission generates. ? uart0 reception, uart2 reception interrupts these are interrupts that the serial i/o reception generates. ? multi-master i 2 c-bus interface 0 and multi-master i 2 c-bus interface 1 interrupts this is an interrupt that the serial i/o transmission/reception is completed, or a stop condition is detected. ? timer a0 interrupt through timer a4 interrupt these are interrupts that timer a generates ? timer b0 interrupt through timer b2 interrupt these are interrupts that timer b generates. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 39 rev. 1.0 ________ ________ ? int 0 interrupt and int 1 interrupt ______ ______ an int interrupt occurs if either a rising edge or a falling edge or a both edge is input to the int pin. ? osd1 interrupt and osd2 interrupt these are interrupts that osd display is completed. ? data slicer interrupt this is an interrupt that data slicer circuit requests. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 40 rev. 1.0 2.7.4 interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure 2.7.2 shows the format for specifying the address. two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. figure 2.7.2 format for specifying interrupt vector addresses aaaaaaaa aaaaaaaa mid address aaaaaaaa aaaaaaaa low address aaaaaaaa aaaaaaaa 0 0 0 0 high address aaaaaaaa aaaaaaaa 0 0 0 0 0 0 0 0 vector address + 0 vector address + 1 vector address + 2 vector address + 3 lsb msb (1) fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 2.7.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. interrupt source vector table addresses remarks address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction overflow fffe0 16 to fffe3 16 interrupt on into instruction brk instruction fffe4 16 to fffe7 16 if the vector is filled with ff 16 , program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 there is an address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use watchdog timer ffff0 16 to ffff3 16 ________ dbc (note) ffff4 16 to ffff7 16 do not use reserved source fffe8 16 to fffeb 16 do not use reset ffffc 16 to fffff 16 note: interrupts used for debugging purposes only. table 2.7.1 interrupts assigned to the fixed vector tables and addresses of vector tables M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 41 rev. 1.0 (2) variable vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 2.7.2 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. table 2.7.2 interrupts assigned to the variable vector tables and addresses of vector tables s o f t w a r e i n t e r r u p t n u m b e ri n t e r r u p t s o u r c e v e c t o r t a b l e a d d r e s s a d d r e s s ( l ) t o a d d r e s s ( h ) r e m a r k s c a n n o t b e m a s k e d i f l a g + 0 t o + 3 ( n o t e )b r k i n s t r u c t i o n s o f t w a r e i n t e r r u p t n u m b e r 0 + 4 4 t o + 4 7 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 1 1 + 4 8 t o + 5 1 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 1 2 + 5 2 t o + 5 5 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 1 3 + 5 6 t o + 5 9 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 1 4 + 6 8 t o + 7 1 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 1 7 + 7 2 t o + 7 5 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 1 8 + 7 6 t o + 7 9 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 1 9 + 8 0 t o + 8 3 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 2 0 + 8 4 t o + 8 7 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 2 1 + 8 8 t o + 9 1 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 2 2 + 9 2 t o + 9 5 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 2 3 + 9 6 t o + 9 9 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 2 4 + 1 0 0 t o + 1 0 3 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 2 5 + 1 0 4 t o + 1 0 7 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 2 6 + 1 0 8 t o + 1 1 1 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 2 7 + 1 1 2 t o + 1 1 5 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 2 8 + 1 1 6 t o + 1 1 9 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 2 9 + 1 2 0 t o + 1 2 3 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 3 0 + 1 2 4 t o + 1 2 7 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 3 1 + 1 2 8 t o + 1 3 1 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 3 2 + 2 5 2 t o + 2 5 5 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 6 3 t o n o t e : a d d r e s s r e l a t i v e t o a d d r e s s i n i n t e r r u p t t a b l e r e g i s t e r ( i n t b ) . c a n n o t b e m a s k e d i f l a g + 4 0 t o + 4 3 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 1 0 + 6 0 t o + 6 3 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 1 5 + 6 4 t o + 6 7 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 1 6 + 2 0 t o + 2 3 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 5 + 2 4 t o + 2 7 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 6 + 2 8 t o + 3 1 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 7 + 3 2 t o + 3 5 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 8 + 1 6 t o + 1 9 ( n o t e ) o s d 1 s o f t w a r e i n t e r r u p t n u m b e r 4 + 3 6 t o + 3 9 ( n o t e ) s o f t w a r e i n t e r r u p t n u m b e r 9 o s d 2 t o d m a 0 d m a 1 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 0 a - d c o n v e r s i o n u a r t 0 t r a n s m i t u a r t 0 r e c e i v e d a t a s l i c e r v s y n c t i m e r a 0 t i m e r a 1 t i m e r a 2 t i m e r a 3 t i m e r a 4 t i m e r b 0 t i m e r b 1 t i m e r b 2 i n t 0 i n t 1 s o f t w a r e i n t e r r u p t b u s c o l l i s i o n d e t e c t i o n u a r t 2 t r a n s m i t u a r t 2 r e c e i v e r e s e r v e d s o u r c e r e s e r v e d s o u r c e r e s e r v e d s o u r c e r e s e r v e d s o u r c e m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 42 rev. 1.0 2.7.5 interrupt control descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. what is described here does not apply to non-maskable interrupts. enable or disable a non-maskable interrupt using the interrupt enable flag (i flag), interrupt priority level selection bit, or processor interrupt priority level (ipl). whether an interrupt request is present or absent is indicated by the interrupt request bit. the interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. also, the interrupt enable flag (i flag) and the ipl are located in the flag register (flg). figure 2.7.3 shows the interrupt control registers. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 43 rev. 1.0 figure 2.7.3 interrupt control registers symbol address when reset intiic(i = 0, 1) 005d 16 , 005e 16 xx00?000 2 iic1ic 0049 16 xx00?000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ilvl0 ir pol nothing is assigned. in an attempt to write to these bits, write ?.?the value, if read, turns out to be indeterminate. interrupt priority level select bit interrupt request bit polarity select bit (note 2) reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge 1 : selects rising edge must always be set to ? ilvl1 ilvl2 notes 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). 2: bit 4 at address 0049 16 is invalid. must always be set to ?.? 3: to rewrite the interrupt control register, do so at a point that does not generate the interrupt register for that register. for details, see the precautions for interrupts. (note 1) interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 bit name function bit symbol w r symbol address when reset osdiic(i = 1, 2) 0044 16 , 0048 16 xxxx?000 2 bcnic 004a 16 xxxx?000 2 dmiic(i = 0, 1) 004b 16 , 004c 16 xxxx?000 2 iic0ic 004d 16 xxxx?000 2 adic 004e 16 xxxx?000 2 sitic(i = 0 , 2) 0051 16 , 004f 16 xxxx?000 2 siric(i = 0 , 2) 0052 16 , 0050 16 xxxx?000 2 dsic 0053 16 xxxx?000 2 vsyncic 0054 16 xxxx?000 2 taiic(i = 0 to 4) 0055 16 to 0059 16 xxxx?000 2 tbiic(i = 0 to 2) 005a 16 to 005c 16 xxxx?000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. in an attempt to write to these bits, write ?.?the value, if read, turns out to be indeterminate. (note) notes 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). 2: to rewrite the interrupt control register, do so at a point that does not generate the interrupt register for that register. for details, see the precautions for interrupts. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 44 rev. 1.0 2.7.6 interrupt enable flag (i flag) the interrupt enable flag (i flag) controls the enabling and disabling of maskable interrupts. setting this flag to 1 enables all maskable interrupts; setting it to 0 disables all maskable interrupts. this flag is set to 0 after reset. 2.7.7 interrupt request bit the interrupt request bit is set to "1" by hardware when an interrupt is requested. after the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. the interrupt request bit can also be set to "0" by software. (do not set this bit to "1"). 2.7.8 interrupt priority level select bit and processor interrupt priority level (ipl) set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. when an interrupt request occurs, the interrupt priority level is compared with the ipl. the interrupt is enabled only when the priority level of the interrupt is higher than the ipl. therefore, setting the interrupt priority level to 0 disables the interrupt. table 2.7.3 shows the settings of interrupt priority levels and table 2.7.4 shows the interrupt levels en- abled, according to the consist of the ipl. the following are conditions under which an interrupt is accepted: interrupt enable flag (i flag) = 1 interrupt request bit = 1 interrupt priority level > ipl the interrupt enable flag (i flag), the interrupt request bit, the interrupt priority select bit, and the ipl are independent, and they are not affected by one another. table 2.7.4 interrupt levels enabled according to the contents of the ipl table 2.7.3 settings of interrupt priority levels interrupt priority level select bit interrupt priority level priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high b2 b1 b0 enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 2 ipl 1 ipl 0 ipl M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 45 rev. 1.0 example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. 2.7.9 rewrite interrupt control register to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 46 rev. 1.0 2.7.10 interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading ad- dress 00000 16 . (2) saves the content of the flag register (flg) as it was immediately before the start of interrupt se- quence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) to 0 (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed) (4) saves the content of the temporary register (note 1) within the cpu in the stack area. (5) saves the content of the program counter (pc) in the stack area. (6) sets the interrupt priority level of the accepted instruction in the ipl. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. 2.7.11 interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 2.7.4 shows the interrupt response time. instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated figure 2.7.4 interrupt response time M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 47 rev. 1.0 interrupt sources without priority levels 7 value set in the ipl watchdog timer other not changed 0 2.7.12 variation of ipl when interrupt request is accepted if an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. if an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in table 2.7.6 is set in the ipl. table 2.7.6 relationship between interrupts without interrupt priority levels and ipl stack pointer (sp) value interrupt vector address 16-bit bus, without wait 8-bit bus, without wait even even odd (note 2) odd (note 2) even odd even odd 18 cycles (note 1) 19 cycles (note 1) 19 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) table 2.7.5 time required for executing the interrupt sequence reset indeterminate 123456789 1011 12 13 14 15 16 17 18 the indeterminate segment is dependent on the queue buffer. if the queue buffer is ready to take an instruction, a read cycle occurs. indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 indeterminate sp-2 sp-4 vec vec+2 pc bclk address bus data bus w r time (a) is dependent on the instruction under execution. thirty cycles is the maximum required for the divx instruction (without wait). time (b) is as shown in table 2.7.5. ________ notes 1: add 2 cycles in the case of a dbc interrupt; add 1 cycle in the case either of an address coinci- dence interrupt or of a single-step interrupt. 2: locate an interrupt vector address in an even address, if possible. figure 2.7.5 time required for executing the interrupt sequence M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 48 rev. 1.0 2.7.13 saving registers in the interrupt sequence, only the contents of the flag register (flg) and that of the program counter (pc) are saved in the stack area. first, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the flg register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. figure 2.7.6 shows the state of the stack as it was before the acceptance of the inter- rupt request, and the state the stack after the acceptance of the interrupt request. save other necessary registers at the beginning of the interrupt routine using software. using the pushm instruction alone can save all the registers except the stack pointer (sp). address content of previous stack stack area [sp] stack pointer value before interrupt occurs m m ?1 m ?2 m ?3 m ?4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m ?1 m ?2 m ?3 m ?4 address flag register (flg l ) content of previous stack stack area flag register (flg h ) program counter (pc h ) [sp] new stack pointer value content of previous stack m + 1 msb lsb program counter (pc l ) program counter (pc m ) figure 2.7.6 state of stack before and after acceptance of interrupt request M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 49 rev. 1.0 the operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. if the content of the stack pointer (note) is even, the content of the flag register (flg) and the content of the program counter (pc) are saved, 16 bits at a time. if odd, their contents are saved in two steps, 8 bits at a time. figure 2.7.7 shows the operation of the saving registers. note: stack pointer indicated by u flag. figure 2.7.7 operation of saving registers (2) stack pointer (sp) contains odd number [sp] (odd) [sp] ?1 (even) [sp] ?2(odd) [sp] ?3 (even) [sp] ?4(odd) [sp] ?5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) stack pointer (sp) contains even number [sp] (even) [sp] ?1(odd) [sp] ?2 (even) [sp] ?3(odd) [sp] ?4 (even) [sp] ?5 (odd) note: [sp] denotes the initial value of the stack pointer (sp) when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) saved simultaneously, all 8 bits flag register (flg h ) program counter (pc h ) flag register (flg h ) program counter (pc h ) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 50 rev. 1.0 2.7.14 returning from an interrupt routine executing the reit instruction at the end of an interrupt routine returns the contents of the flag register (flg) as it was immediately before the start of interrupt sequence and the contents of the program counter (pc), both of which have been saved in the stack area. then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process re- sumes. return the other registers saved by software within the interrupt routine using the popm or similar in- struction before executing the reit instruction. 2.7.15 interrupt priority if there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. assign an arbitrary priority to maskable interrupts (peripheral i/o interrupts) using the interrupt priority level select bit. if the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. priorities of the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. figure 2.7.8 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. 2.7.16 interrupt priority level resolution circuit when two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. figure 2.7.9 shows the circuit that judges the interrupt priority level. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 51 rev. 1.0 figure 2.7.8 hardware interrupts priorities ________ reset > dbc > watchdog timer > peripheral i/o > single step > address match figure 2.7.9 maskable interrupts priorities (peripheral i/o interrupts) v s y n c u a r t 0 r e c e p t i o n u a r t 2 r e c e p t i o n a - d c o n v e r s i o n d m a 1 b u s c o l l i s i o n d e t e c t i o n t i m e r a 0 d a t a s l i c e r u a r t 0 t r a n s m i s s i o n u a r t 2 t r a n s m i s s i o n p r i o r i t y o f p e r i p h e r a l i / o i n t e r r u p t s ( i f p r i o r i t y l e v e l s a r e s a m e ) o s d 2 t i m e r b 2 t i m e r b 0 t i m e r a 3 t i m e r a 1 t i m e r b 1 t i m e r a 4 t i m e r a 2 i n t 1 i n t 0 l e v e l 0 ( i n i t i a l v a l u e ) p r i o r i t y l e v e l o f e a c h i n t e r r u p t h i g h o s d 1 l o w d m a 0 i n t e r r u p t e n a b l e f l a g ( i f l a g ) w a t c h d o g t i m e r r e s e t d b c i n t e r r u p t r e q u e s t a c c e p t e d a d d r e s s m a t c h p r o c e s s o r i n t e r r u p t p r i o r i t y l e v e l ( i p l ) m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 0 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e 1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 52 rev. 1.0 ______ 2.7.17 int interrupt ________ ________ int 0 and int 1 are triggered by the edges of external inputs. the edge polarity is selected using the polarity select bit. as for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting 1 in the inti interrupt polarity switching bit of the interrupt request cause select register (035f 16 ). to select both edges, set the polarity switching bit of the corresponding interrupt control regis- ter to falling edge (0). figure 2.7.10 shows the interrupt control reserved register, figure 2.7.11 shows the interrupt request cause select register. figure 2.7.10 interrupt control reserved register i (i = 0 to 3) i n t e r r u p t c o n t r o l r e s e r v e d r e g i s t e r i b i t n a m ef u n c t i o n b i t s y m b o l w r s y m b o la d d r e s sw h e n r e s e t r e i i c ( i = 0 t o 3 ) 0 0 4 5 1 6 , 0 0 4 6 1 6 , 0 0 4 7 1 6 , 0 0 5 f 1 6 i n d e t e r m i n a t e b 7b 6b 5b 4b 3b 2b 1b 0 m u s t a l w a y s b e s e t t o 0 r e s e r v e d b i t s 0 0000000 figure 2.7.11 interrupt request cause select register i n t e r r u p t r e q u e s t c a u s e s e l e c t r e g i s t e r b i t n a m ef u n c t i o n b i t s y m b o l w r s y m b o la d d r e s sw h e n r e s e t i f s r 0 3 5 f 1 6 0 0 1 6 i f s r 0 b 7b 6b 5b 4b 3b 2b 1b 0 i n t 0 i n t e r r u p t p o l a r i t y s w i t c h i n g b i t 0 : o n e e d g e 1 : t w o e d g e s 0 : o n e e d g e 1 : t w o e d g e s m u s t a l w a y s b e s e t t o 0 i n t 1 i n t e r r u p t p o l a r i t y s w i t c h i n g b i t r e s e r v e d b i t s i f s r 1 0 000 00 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 53 rev. 1.0 2.7.18 address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not af- fected by the interrupt enable flag (i flag) and processor interrupt priority level (ipl). the value of the program counter (pc) for an address match interrupt varies depending on the instruction being executed. figures 2.7.12 and 2.7.13 show the address match interrupt-related registers. bit name bit symbol symbol address when reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function w r address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 symbol address when reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminated. b7 b6 b5 b4 b3 b2 b1 b0 w r address setting register for address match interrupt function values that can be set address match interrupt register i (i = 0, 1) 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminated. 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) figure 2.7.13 address match interrupt register i (i = 0, 1) figure 2.7.12 address match interrupt enable register M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 54 rev. 1.0 2.7.19 precautions for interrupts (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. (3) external interrupt ________ ? either an l level or an h level of at least 250 ns width is necessary for the signal input to pins int 0 _______ and int 1 regardless of the cpu operation clock. _______ _______ ?when the polarity of the int 0 and int 1 pins is changed, the interrupt request bit is sometimes set to 1. after changing the polarity, set the interrupt request bit to 0. figure 2.7.14 shows the procedure ______ for changing the int interrupt generate factor. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 55 rev. 1.0 ______ figure 2.7.14 switching condition of int interrupt request set the polarity select bit clear the interrupt request bit to ? set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) clear the interrupt enable flag to ? (disable interrupt) set the interrupt enable flag to ? (enable interrupt) example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. (4) rewrite interrupt control register ? to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control regis- ter after the interrupt is disabled. the program examples are described as follow: ? when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 56 rev. 1.0 2.8 watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the bclk using the prescaler. a watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). thus the watchdog timers period can be calculated as given below. the watchdog timers period is, however, subject to an error due to the pre-scaler. watchdog timer period = for example suppose that bclk runs at 10 mhz and that 16 has been chosen for the dividing ratio of the pre-scaler, then the watchdog timers period becomes approximately 52.4 ms. the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the microcomputer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). figure 2.8.1 shows the block diagram of the watchdog timer. figure 2.8.2 shows the watchdog timer control register and figure 2.8.3 shows the watchdog timer start register. pre-scaler dividing ratio (16 or 128) 5 watchdog timer count (32768) bclk M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 57 rev. 1.0 figure 2.8.3 watchdog timer start register watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to ?fff 16 regardless of whatever value is written. figure 2.8.1 block diagram of watchdog timer figure 2.8.2 watchdog timer control register watchdog timer control register symbol address when reset wdc 000f 16 000????? 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 reserved bits must always be set to ? 0 0 bclk write to the watchdog timer start register (address 000e 16 ) reset watchdog timer interrupt request watchdog timer set to 7fff 16 1/16 wdc7 = 0 wdc7 = 1 hold 1/128 prescaler M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 58 rev. 1.0 2.9 dmac this microcomputer has two dmac (direct memory access controller) channels that allow data to be sent to memory without using the cpu. dmac shares the same data bus with the cpu. the dmac is given a higher right of using the bus than the cpu, which leads to working the cycle stealing method. on this account, the operation from the occurrence of dma transfer request signal to the completion of 1-word (16- bit) or 1-byte (8-bit) data transfer can be performed at high speed. figure 2.9.1 shows the block diagram of the dmac. table 2.9.1 shows the dmac specifications. figures 2.9.2 to 2.9.7 show the registers used by the dmac. figure 2.9.1 block diagram of dmac data bus low-order bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) data bus high-order bits address bus dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: pointer is incremented by a dma request. either a write signal to the software dma request bit or an interrupt request signal is used as a dma transfer request signal. but the dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. the dma transfer doesn't affect any interrupts either. if the dmac is active (the dma enable bit is set to 1), data transfer starts every time a dma transfer request signal occurs. if the cycle of the occurrences of dma transfer request signals is higher than the dma transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. for details, see the description of the dma request bit. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 59 rev. 1.0 item specification no. of channels 2 (cycle steal method) transfer memory space ? from any address in the 1m bytes space to a fixed address ? from a fixed address to any address in the 1m bytes space ? from a fixed address to a fixed address (note that dma-related registers [0020 16 to 003f 16 ] cannot be accessed) maximum no. of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors (note) ________ falling edge or both edge of pin int 0 _______ falling edge of pin int 1 timer a0 to timer a4 interrupt requests timer b0 to timer b2 interrupt requests uart0 transmission and reception interrupt requests uart2 transmission and reception interrupt requests multi-master i 2 c-bus interface 0 interrupt request multi-master i 2 c-bus interface 1 interrupt request a-d conversion interrupt request osd1 and osd2 interrupt requests data slicer interrupt request v sync interrupt request software triggers channel priority dma0 takes precedence if dma0 and dma1 requests are generated simultaneously transfer unit 8 bits or 16 bits transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) transfer mode ? single transfer mode after the transfer counter underflows, the dma enable bit turns to 0, and the dmac turns inactive ? repeat transfer mode after the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. the dmac remains active unless a 0 is written to the dma enable bit. dma interrupt request generation timing when an underflow occurs in the transfer counter active when the dma enable bit is set to 1, the dmac is active. when the dmac is active, data transfer starts every time a dma transfer request signal occurs. inactive ? when the dma enable bit is set to 0, the dmac is inactive. ? after the transfer counter underflows in single transfer mode forward address pointer and at the time of starting data transfer immediately after turning the dmac active, reload timing for transfer counter the value of one of source pointer and destination pointer - the one specified for the forward direction - is reloaded to the forward direction address pointer, and the value of the transfer counter reload register is reloaded to the transfer counter. writing to register registers specified for forward direction transfer are always write enabled. registers specified for fixed address transfer are write-enabled when the dma enable bit is 0. reading the register can be read at any time. however, when the dma enable bit is 1, reading the register set up as the forward register is the same as reading the value of the forward address pointer. table 2.9.1 dmac specifications note: dma transfer is not effective to any interrupt. dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 60 rev. 1.0 figure 2.9.2 dma0 request cause select register dma0 request cause select register symbol address when reset dm0sl 03b8 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. in an attempt to write to these bits, write ?.? the value, if read, turns out to be ?. software dma request bit if software trigger is selected, a dma request is generated by setting this bit to ?? (when read, the value of this bit is always ?? dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int 0 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3 0 1 1 0 : timer a4 (dms = 0) /two edges of int 0 pin (dms=1) 0 1 1 1 : timer b0 (dms = 0) /osd1 (dms=1) 1 0 0 0 : timer b1 (dms = 0) /osd2 (dms=1) 1 0 0 1 : timer b2 (dms = 0) /multi-master i 2 c-bus interface 0 (dms=1) 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : data slicer bit name dms dma request cause expansion bit 0 : normal 1 : expanded cause M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 61 rev. 1.0 figure 2.9.3 dma1 request cause select register figure 2.9.4 dmai control register (i = 0, 1) d m a i c o n t r o l r e g i s t e r s y m b o l a d d r e s s w h e n r e s e t d m i c o n ( i = 0 , 1 ) 0 0 2 c 1 6 , 0 0 3 c 1 6 0 0 0 0 0 ? 0 0 2 b i t n a m ef u n c t i o n b i t s y m b o l t r a n s f e r u n i t b i t s e l e c t b i t b 7b 6b 5b 4b 3b 2b 1b 0 0 : 1 6 b i t s 1 : 8 b i t s d m b i t r w d m a s l d m a s d m a e r e p e a t t r a n s f e r m o d e s e l e c t b i t 0 : s i n g l e t r a n s f e r 1 : r e p e a t t r a n s f e r d m a r e q u e s t b i t ( n o t e 1 ) 0 : d m a n o t r e q u e s t e d 1 : d m a r e q u e s t e d 0 : d i s a b l e d 1 : e n a b l e d 0 : f i x e d 1 : f o r w a r d d m a e n a b l e b i t s o u r c e a d d r e s s d i r e c t i o n s e l e c t b i t ( n o t e 3 ) d e s t i n a t i o n a d d r e s s d i r e c t i o n s e l e c t b i t ( n o t e 3 ) 0 : f i x e d 1 : f o r w a r d d s d d a d n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 . n o t e s 1 : d m a r e q u e s t c a n b e c l e a r e d b y r e s e t t i n g t h e b i t . 2 : t h i s b i t c a n o n l y b e s e t t o 0 . 3 : s o u r c e a d d r e s s d i r e c t i o n s e l e c t b i t a n d d e s t i n a t i o n a d d r e s s d i r e c t i o n s e l e c t b i t c a n n o t b e s e t t o 1 s i m u l t a n e o u s l y . ( n o t e 2 ) dma1 request cause select register symbol address when reset dm1sl 03ba 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 software dma request bit if software trigger is selected, a dma request is generated by setting this bit to ?? (when read, the value of this bit is always ?? dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int 1 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3 (dms = 0) /osd1 (dms = 1) 0 1 1 0 : timer a4 (dms = 0) /osd2 (dms = 1) 0 1 1 1 : timer b0 /multi-master i 2 c-bus interface 1 (dms = 1) 1 0 0 0 : timer b1 1 0 0 1 : timer b2 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : v sync bit name 0 : normal 1 : expanded cause dma request cause expansion bit dms nothing is assigned. in an attempt to write to these bits, write ?.? the value, if read, turns out to be ?. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 62 rev. 1.0 b7 b0 b7 b0 (b8) (b15) function rw ? transfer counter set a value one less than the transfer count symbol address when reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) transfer count specification 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw ? source pointer stores the source address symbol address when reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. symbol address when reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function rw ? destination pointer stores the destination address dmai destination pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 b7 (b23) nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. figure 2.9.5 dmai source pointer (i = 0, 1) figure 2.9.6 dmai destination pointer (i = 0, 1) figure 2.9.7 dmai transfer counter (i = 0, 1) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 63 rev. 1.0 2.9.1 transfer cycle the transfer cycle consists of the bus cycle in which data is read from memory or from the sfr area (source read) and the bus cycle in which the data is written to memory or to the sfr area (destination write). the number of read and write bus cycles depends on the source and destination addresses. also, the bus cycle itself is longer when software waits are inserted. (1) effect of source and destination addresses when 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (2) effect of software wait when the sfr area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. the length of the cycle is determined by bclk. figure 2.9.8 shows the example of the transfer cycles for a source read. for convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating the transfer cycle, remember to apply the respec- tive conditions to both the destination write cycle and the source read cycle. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 64 rev. 1.0 figure 2.9.8 example of the transfer cycles for a source read bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1)16-bit transfers from even address and the source address is even. bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (3) one wait is inserted into the source read under the conditions in (1) bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) 16-bit transfers and the source address is odd bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (4) one wait is inserted into the source read under the conditions in (2) note: the same timing changes occur with the respective conditions at the destination as at the source. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 65 rev. 1.0 table 2.9.2 no. of dmac transfer cycles 2.9.2 dmac transfer cycles any combination of even or odd transfer read and write addresses is possible. table 2.9.2 shows the number of dmac transfer cycles. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles 5 j + no. of write cycles 5 k internal memory internal rom/ram internal rom/ram sfr area /osd ram no wait with wait no wait 122 coefficient j, k single-chip mode transfer unit bus width access address no. of read cycles no. of write cycles 8-bit transfers 16-bit even 1 1 (dmbit= 1) odd 1 1 16-bit transfers 16-bit even 1 1 (dmbit= 0) odd 2 2 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 66 rev. 1.0 2.9.3 dma enable bit setting the dma enable bit to 1 makes the dmac active. the dmac carries out the following operations at the time data transfer starts immediately after dmac is turned active. (1) reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) reloads the value of the transfer counter reload register to the transfer counter. thus overwriting 1 to the dma enable bit with the dmac being active carries out the operations given above, so the dmac operates again from the initial state at the instant 1 is overwritten to the dma enable bit. 2.9.4 dma request bit the dmac can generate a dma transfer request signal triggered by a factor chosen in advance out of dma request factors for each channel. dma request factors include the following. * factors effected by using the interrupt request signals from the built-in peripheral functions and software dma factors (internal factors) effected by a program. * external factors effected by utilizing the input from external interrupt signals. for the selection of dma request factors, see the descriptions of the dmai factor selection register. the dma request bit turns to 1 if the dma transfer request signal occurs regardless of the dmacs state (regardless of whether the dma enable bit is set 1 or to 0). it turns to 0 immediately before data transfer starts. in addition, it can be set to 0 by use of a program, but cannot be set to 1. there can be instances in which a change in dma request factor selection bit causes the dma request bit to turn to 1. so be sure to set the dma request bit to 0 after the dma request factor selection bit is changed. the dma request bit turns to 1 if a dma transfer request signal occurs, and turns to 0 immediately before data transfer starts. if the dmac is active, data transfer starts immediately, so the value of the dma request bit, if read by use of a program, turns out to be 0 in most cases. to examine whether the dmac is active, read the dma enable bit. here follows the timing of changes in the dma request bit. (1) internal factors except the dma request factors triggered by software, the timing for the dma request bit to turn to 1 due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to 1 due to several factors. turning the dma request bit to 1 due to an internal factor is timed to be effected immediately before the transfer starts. (2) external factors _______ an external factor is a factor caused to occur by the leading edge of input from the inti pin (i depends on which dmac channel is used). _______ selecting the inti pins as external factors using the dma request factor selection bit causes input from these pins to become the dma transfer request signals. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 67 rev. 1.0 the timing for the dma request bit to turn to 1 when an external factor is selected synchronizes with the signals edge applicable to the function specified by the dma request factor selection bit (synchro- _______ nizes with the trailing edge of the input signal to each inti pin, for example). with an external factor selected, the dma request bit is timed to turn to 0 immediately before data transfer starts similarly to the state in which an internal factor is selected. (3) the priorities of channels and dma transfer timing if a dma transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of bclk), the dma request bits of applicable channels concurrently turn to 1. if the channels are active at that moment, dma0 is given a high priority to start data transfer. when dma0 finishes data transfer, it gives the bus right to the cpu. when the cpu finishes single bus access, then dma1 starts data transfer and gives the bus right to the cpu. figure 2.9.9 illustrates these operations. an example in which dma transfer is carried out in minimum cycles at the time when dma transfer request signals due to external factors concurrently occur. bclk aaaa aaaa dma0 aaaa dma1 dma0 request bit dma1 request bit aaa aaa aaaaa aaaaa a a aaaaaa aaaaaa aa aa cpu int0 int1 obtainm ent of the bus right an example in which dma transmission is carried out in minimum cycles at the time when dma transmission request signals due to external factors concurrently occur. figure 2.9.9 an example of dma transfer effected by external factors M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 68 rev. 1.0 2.10 timer there are eight 16-bit timers. these timers can be classified by function into timers a (five) and timers b (three). all these timers function independently. figures 2.10.1 and 2.10.2 show the block diagram of timers. figure 2.10.1 timer a block diagram ?timer mode ?one-shot mode ?timer mode ?one-shot mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode timer a0 timer a1 timer a2 timer a3 timer a4 f 1 f 8 f 32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt 1/8 1/4 f 1 f 8 f 32 x in timer b2 overflow M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 69 rev. 1.0 figure 2.10.2 timer b block diagram ?event counter mode ?event counter mode ?event counter mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode tb0 in timer b0 timer b1 timer b2 f 1 f 8 f 32 timer b0 interrupt noise filter 1/8 1/4 f 1 f 8 f 32 x in timer a timer b1 interrupt timer b2 interrupt M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 70 rev. 1.0 2.10.1 timer a figure 2.10.3 shows the block diagram of timer a. figures 2.10.4 to 2.10.10 show the timer a-related registers. except the pulse output function, timers a0 through a4 all have the same function. use the timer ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. timer a has the four operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts a timer over flow. ? one-shot timer mode: the timer stops counting when the count reaches 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses of a given width. timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit figure 2.10.3 block diagram of timer a figure 2.10.4 timer ai mode register (i = 0 to 4) count start flag (address 0380 16 ) up count/down count tai addresses taj tak timer a0 0387 16 0386 16 timer a4 timer a1 timer a1 0389 16 0388 16 timer a0 timer a2 timer a2 038b 16 038a 16 timer a1 timer a3 timer a3 038d 16 038c 16 timer a2 timer a4 timer a4 038f 16 038e 16 timer a3 timer a0 always down count except in event counter mode reload register (16) counter (16) low-order 8 bits high-order 8 bits clock source selection ?timer ?one shot ?pwm f 1 f 8 f 32 external trigger tb2 overflow clock selection taj overflow (j = i ?1. note, however, that j = 4 when i = 0) pulse output toggle flip-flop tai out (i = 2, 3) data bus low-order bits data bus high-order bits up/down flag down count (address 0384 16 ) tak overflow (k = i + 1. note, however, that k = 0 when i = 4) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 71 rev. 1.0 symbol address when reset ta0 0387 16 ,0386 16 indeterminate ta1 0389 16 ,0388 16 indeterminate ta2 038b 16 ,038a 16 indeterminate ta3 038d 16 ,038c 16 indeterminate ta4 038f 16 ,038e 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer ai register (note) w r ?timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set ?event counter mode 0000 16 to ffff 16 counts pulses from an timer overflow ?one-shot timer mode 0000 16 to ffff 16 counts a one shot width ?pulse width modulation mode (16-bit pwm) (ta2, ta3) functions as a 16-bit pulse width modulator ?pulse width modulation mode (8-bit pwm) (ta2, ta3) timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 00 16 to fe 16 (both high-order and low-order addresses) 0000 16 to fffe 16 note: read and write data in 16-bit units. symbol address when reset tabsr 0380 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s figure 2.10.6 count start flag figure 2.10.5 timer ai register (i = 0 to 4) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 72 rev. 1.0 figure 2.10.7 up/down flag timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag symbol address when reset udf 0384 16 00 16 reserved bit up/down flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud must always be set to ?? 000 this specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : down count 1 : up count ta1os ta2os ta0os one-shot start flag symbol address when reset onsf 0382 16 00x00000 2 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. this bit can neither be set nor reset. when read, its content is indeterminate. ta0tgl ta0tgh 0 0 : do not set 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 w r 1 : timer start when read, the value is ? figure 2.10.8 one-shot start flag M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 73 rev. 1.0 figure 2.10.10 reserved register 6 ta1tgl symbol address when reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : do not set 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : do not set 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : do not set 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : do not set 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 symbol address when reset invc6 0381 16 0xxxxxxx 2 reserved register 6 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 must always be set to ?. reserved bit w r nothing is assigned. in an attempt to write to these bits, write ?.?the value, if read, turns out to be indeterminate. 0 figure 2.10.9 trigger select register M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 74 rev. 1.0 notes 1 : the settings of the corresponding port register and port direction register are invalid. 2 : this bit of taimr (i = 0, 1, 4) must always be set to ?. timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit (note 2) 0 : pulse is not output (ta2 out /ta3 out pin is a normal port pin) 1 : pulse is output (note 1) (ta2 out /ta3 out pin is a pulse output pin) must always be set to ? reserved bits mr3 0 (must always be set to ??in timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : do not set b7 b6 tck1 tck0 count source select bit 00 0 00 figure 2.10.11 timer ai mode register in timer mode (i = 0 to 4) (1) timer mode in this mode, the timer counts an internally generated count source. (see table 2.10.1.) figure 2.10.11 shows the timer ai mode register in timer mode. table 2.10.1 specifications of timer mode item specification count source f 1 , f 8 , f 32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when the timer underflows ta2 out /ta3 out pin function programmable i/o port or pulse output read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? pulse output function each time the timer underflows, the tai out pins polarity is reversed M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 75 rev. 1.0 (2) event counter mode in this mode, the timer counts an internal timers overflow. table 2.10.2 timer specifications in event counter mode item specification count source ? tb2 overflow, taj overflow, tak overflow count operation ? up count or down count can be selected by external signal or software ? when the timer overflows or underflows, it reloads the reload register contents before continuing counting (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer overflows or underflows ta2 out /ta3 out pin function programmable i/o port, pulse output, or up/down count select input read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ? pulse output function each time the timer overflows or underflows, the tai out pins polarity is reversed note: this does not apply when the free-run function is selected. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 76 rev. 1.0 t i m e r a i m o d e r e g i s t e r s y m b o l a d d r e s s w h e n r e s e t t a i m r ( i = 0 t o 4 ) 0 3 9 6 1 6 t o 0 3 9 a 1 6 0 0 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 1 : e v e n t c o u n t e r m o d e ( n o t e 1 ) b 1 b 0 t m o d 1 t m o d 0 m r 0 p u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : p u l s e i s n o t o u t p u t ( t a 2 o u t / t a 3 o u t p i n i s a n o r m a l p o r t p i n ) 1 : p u l s e i s o u t p u t ( n o t e 2 ) ( t a 2 o u t / t a 3 o u t p i n i s a p u l s e o u t p u t p i n ) r e s e r v e d b i t m r 3 0 : ( m u s t a l w a y s b e s e t t o 0 i n e v e n t c o u n t e r m o d e ) r e s e r v e d b i t t c k 0 01 0 m u s t a l w a y s b e s e t t o 0 b i t s y m b o lb i t n a m ef u n c t i o n w r c o u n t o p e r a t i o n t y p e s e l e c t b i t 0 : r e l o a d t y p e 1 : f r e e - r u n t y p e m u s t a l w a y s b e s e t t o 0 00 n o t e s 1 : i n e v e n t c o u n t e r m o d e , t h e c o u n t s o u r c e i s s e l e c t e d b y t h e e v e n t / t r i g g e r s e l e c t b i t ( a d d r e s s e s 0 3 8 2 1 6 a n d 0 3 8 3 1 6 ) . 2 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d . 3 : t h i s b i t o f t a i m r ( i = 0 , 1 , 4 ) m u s t a l w a y s b e s e t t o 0 . 4 : w h e n a n l s i g n a l i s i n p u t t o t h e i n p u t s i g n a l f r o m t a 2 o u t / t a 3 o u t p i n , t h e d o w n c o u n t i s a c t i v a t e d . w h e n h , t h e u p c o u n t i s a c t i v a t e d . s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . m r 2 u p / d o w n s w i t c h i n g c a u s e s e l e c t b i t 0 : u p / d o w n f l a g s c o n t e n t 1 : t a 2 o u t / t a 3 o u t p i n s i n p u t s i g n a l ( n o t e s 3 , 4 ) figure 2.10.12 timer ai mode register in event counter mode (i = 0 to 4) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 77 rev. 1.0 figure 2.10.13 timer ai mode register in one-shot timer mode (i = 0 to 4) (3) one-shot timer mode in this mode, the timer operates only once. (see table 2.10.3.) when a trigger occurs, the timer starts up and continues operating for a given period. figure 2.10.13 shows the timer ai mode register in one-shot timer mode. table 2.10.3 timer specifications in one-shot timer mode item specification count source f 1 , f 8 , f 32 count operation ? the timer counts down ? when the count reaches 0000 16 , the timer stops counting after reloading a new count ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition ? the timer overflows ? the one-shot start flag is set (= 1) count stop condition ? a new count is reloaded after the count has reached 0000 16 ? the count start flag is reset (= 0) interrupt request generation timing the count reaches 0000 16 ta2 out /ta3 out pin function programmable i/o port or pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) bit name timer ai mode register symbol address when reset taimr(i = 0 to 4) 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit (note 2) 0 : pulse is not output (ta2 out /ta3 out pin is a normal port pin) 1 : pulse is output (note 1) (ta2 out /ta3 out pin is a pulse output pin) reserved bits 10 0 must always be set to ? w r 0 mr3 0 (must always be ??in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : do not set b7 b6 tck1 tck0 count source select bit mr2 trigger select bit 0 : count start flag is valid 1 : selected by event/trigger select register notes 1 : the settings of the corresponding port register and port direction register are invalid. 2 : this bit of taimr (i = 0, 1, 4) must always be set to ?. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 78 rev. 1.0 item specification count source f 1 , f 8 , f 32 count operation ? the timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new count at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs when counting 16-bit pwm ? high level width n / fi n : set value ? cycle time (2 16 -1) / fi fixed 8-bit pwm ? high level width n 5 (m+1) / fi n : values set to timer ai registers high-order address ? cycle time (2 8 -1) 5 (m+1) / fi m : values set to timer ai registers low-order address count start condition ? the timer overflows ? the count start flag is set (= 1) count stop condition ? the count start flag is reset (= 0) interrupt request generation timing pwm pulse goes l ta2 out /ta3 out pin function pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) (4) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 2.10.4.) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure 2.10.14 shows the timer ai mode register in pulse width modulation mode. figure 2.10.15 shows the example of how an 8-bit pulse width modulator operates. table 2.10.4 timer specifications in pulse width modulation mode figure 2.10.14 timer ai mode register in pulse width modulation mode (i = 2 and 3) bit name timer ai mode register symbol address when reset taimr(i=2 and 3) 0398 16 and 0399 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 reserved bits mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : do not set b7 b6 tck1 tck0 count source select bit w r 11 1 1 (must always be ??in pwm mode) 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator must always be set to ? 0 mr2 trigger select bit 0: count start flag is valid 1: selected by event/trigger select register M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 79 rev. 1.0 figure 2.10.15 example of how an 8-bit pulse width modulator operates c o u n t s o u r c e ( n o t e 1 ) t i m e r o v e r f l o w u n d e r f l o w s i g n a l o f 8 - b i t p r e s c a l e r ( n o t e 2 ) p w m p u l s e o u t p u t f r o m t a i o u t p i n h h h l l l 1 0 t i m e r a i i n t e r r u p t r e q u e s t b i t c l e a r e d t o 0 w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r c l e a r e d b y s o f t w a r e f i : f r e q u e n c y o f c o u n t s o u r c e ( f 1 , f 8 , f 3 2 , f c 3 2 ) n o t e s 1 : t h e 8 - b i t p r e s c a l e r c o u n t s t h e c o u n t s o u r c e . 2 : t h e 8 - b i t p u l s e w i d t h m o d u l a t o r c o u n t s t h e 8 - b i t p r e s c a l e r ' s u n d e r f l o w s i g n a l . 3 : m = 0 0 1 6 t o f e 1 6 ; n = 0 0 1 6 t o f e 1 6 . c o n d i t i o n : r e l o a d r e g i s t e r h i g h - o r d e r 8 b i t s = 0 2 1 6 r e l o a d r e g i s t e r l o w - o r d e r 8 b i t s = 0 2 1 6 t i m e r o v e r f l o w i s s e l e c t e d 1 / f i x ( m + 1 ) x ( 2 C 1 ) 8 1 / f i x ( m + 1 ) x n 1 / f i x ( m + 1 ) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 80 rev. 1.0 2.10.2 timer b figure 2.10.17 shows the block diagram of timer b. figures 2.10.17 and 2.10.20 show the timer b-related registers. use the timer bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. timer b has three operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer overflow. ? pulse period/pulse width measuring mode: the timer measures an external signals pulse period or pulse width. figure 2.10.16 block diagram of timer b figure 2.10.17 timer bi mode register (i = 0 to 2) timer bi mode register symbol address when reset tbimr(i = 0 to 2) 039b 16 to 039d 16 00?x0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : inhibited b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit (note 1) (note 2) notes 1: timer b0. 2: timer b1, timer b2. clock source selection (address 0380 16 ) ?event counter ?timer ?pulse period/pulse width measurement reload register (16) low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 f 8 f 32 tbj overflow (j = i ?1. note, however, j = 2 when i = 0) can be selected in only event counter mode count start flag polarity switching and edge pulse tb0 in counter reset circuit counter (16) tbi address tbj timer b0 0391 16 0390 16 timer b2 timer b1 0393 16 0392 16 timer b0 timer b2 0395 16 0394 16 timer b1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 81 rev. 1.0 symbol address when reset tabsr 0380 16 00 16 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function figure 2.10.20 reserved register figure 2.10.18 timer bi register (i = 0 to 2) figure 2.10.19 count start flag symbol address when reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate tb2 0395 16 , 0394 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (note) w r ?pulse period / pulse width measurement mode measures a pulse period or width ?timer mode 0000 16 to ffff 16 counts the timer's period function values that can be set ?event counter mode 0000 16 to ffff 16 counts external pulses input or a timer overflow note: read and write data in 16-bit units. symbol address when reset invc6 0381 16 0xxxxxxx 2 reserved register 6 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 must always be set to ?. reserved bit w r nothing is assigned. in an attempt to write to these bits, write ?.?the value, if read, turns out to be indeterminate. 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 82 rev. 1.0 item specification count source f 1 , f 8 , f 32 count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tb0 in pin function programmable i/o port read from timer count value is read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) (1) timer mode in this mode, the timer counts an internally generated count source. (see table 2.10.5) figure 2.10.21 shows the timer bi mode register in timer mode. table 2.10.5 timer specifications in timer mode figure 2.10.21 timer bi mode register in timer mode (i = 0 to 2) n o t e s 1 : t i m e r b 0 . 2 : t i m e r b 1 , t i m e r b 2 . t i m e r b i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b i m r ( i = 0 t o 2 )0 3 9 b 1 6 t o 0 3 9 d 1 6 0 0 ? x 0 0 0 0 2 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 0 : t i m e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 i n v a l i d i n t i m e r m o d e c a n b e 0 o r 1 m r 2 m r 1 m r 3 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : d o n o t s e t t c k 1 t c k 0 c o u n t s o u r c e s e l e c t b i t 0 i n v a l i d i n t i m e r m o d e . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d i n t i m e r m o d e , t u r n s o u t t o b e i n d e t e r m i n a t e . 0 0 ( f i x e d t o 0 i n t i m e r m o d e ; i = 0 ) n o t h i n g i s a s s i g n e d ( i = 1 , 2 ) . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . ( n o t e 1 ) ( n o t e 2 ) b 7 b 6 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 83 rev. 1.0 item specification count source ? external signals input to tb0 in pin ? effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tb0 in pin function count source input read from timer count value can be read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) table 2.10.6 timer specifications in event counter mode figure 2.10.22 timer bi mode register in event counter mode (i = 0 to 2) (2) event counter mode in this mode, the timer counts an external signal or an internal timers overflow. (see table 2.10.6) figure 2.10.22 shows the timer bi mode register in event counter mode. t i m e r b i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b i m r ( i = 0 t o 2 )0 3 9 b 1 6 t o 0 3 9 d 1 6 0 0 ? x 0 0 0 0 2 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 1 : e v e n t c o u n t e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 c o u n t p o l a r i t y s e l e c t b i t ( n o t e 1 ) m r 2 m r 1 m r 3 t c k 1 t c k 0 01 0 0 : c o u n t s e x t e r n a l s i g n a l ' s f a l l i n g e d g e s 0 1 : c o u n t s e x t e r n a l s i g n a l ' s r i s i n g e d g e s 1 0 : c o u n t s e x t e r n a l s i g n a l ' s f a l l i n g a n d r i s i n g e d g e s 1 1 : i n h i b i t e d b 3 b 2 n o t e s 1 : v a l i d o n l y w h e n i n p u t f r o m t h e t b 0 i n p i n i s s e l e c t e d a s t h e e v e n t c l o c k . i f t i m e r ' s o v e r f l o w i s s e l e c t e d , t h i s b i t c a n b e 0 o r 1 . 2 : t i m e r b 0 . 3 : t i m e r b 1 , t i m e r b 2 . 4 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . i n v a l i d i n e v e n t c o u n t e r m o d e . c a n b e 0 o r 1 . e v e n t c l o c k s e l e c t 0 : i n p u t f r o m t b 0 i n p i n ( n o t e 4 ) 1 : t b j o v e r f l o w ( j = i 1 ; h o w e v e r , j = 2 w h e n i = 0 ) 0 ( f i x e d t o 0 i n e v e n t c o u n t e r m o d e ; i = 0 ) ( n o t e 2 ) ( n o t e 3 ) i n v a l i d i n t i m e r m o d e . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d i n e v e n t c o u n t e r m o d e , t u r n s o u t t o b e i n d e t e r m i n a t e . n o t h i n g i s a s s i g n e d ( i = 1 , 2 ) . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 84 rev. 1.0 table 2.10.7 timer specifications in pulse period/pulse width measurement mode notes 1: an interrupt request is not generated when the first effective edge is input after the timer has started counting. 2: the value read out from the timer b0 register is indeterminate until the second effective edge is input after the timer. (3) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table 2.10.7) figure 2.10.23 shows the timer b0 mode register in pulse period/pulse width measurement mode. figure 2.10.24 shows the operation timing when measuring a pulse period. figure 2.10.25 shows the operation timing when measuring a pulse width. item specification count source f 1 , f 8 , f 32 count operation ? up count ? counter value 0000 16 is transferred to reload register at measurement pulse's effective edge and the timer continues counting count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing ? when measurement pulse's effective edge is input (note 1) ? when an overflow occurs. (simultaneously, the timer bi overflow flag changes to 1. the timer b0 overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer b0 mode register.) tb0 in pin function measurement pulse input read from timer when timer b0 register is read, it indicates the reload registers content (measurement result) (note 2) write to timer cannot be written to figure 2.10.23 timer b0 mode register in pulse period/pulse width measurement mode t i m e r b 0 m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b 0 m r0 3 9 b 1 6 0 0 ? x 0 0 0 0 2 b i t n a m e b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 1 0 : p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 m e a s u r e m e n t m o d e s e l e c t b i t m r 2 m r 1 m r 3 t c k 1 t c k 0 0 1 0 0 : p u l s e p e r i o d m e a s u r e m e n t ( i n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e ' s f a l l i n g e d g e t o f a l l i n g e d g e ) 0 1 : p u l s e p e r i o d m e a s u r e m e n t ( i n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e ' s r i s i n g e d g e t o r i s i n g e d g e ) 1 0 : p u l s e w i d t h m e a s u r e m e n t ( i n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e ' s f a l l i n g e d g e t o r i s i n g e d g e , a n d b e t w e e n r i s i n g e d g e t o f a l l i n g e d g e ) 1 1 : i n h i b i t e d f u n c t i o n b 3 b 2 c o u n t s o u r c e s e l e c t b i t t i m e r b i o v e r f l o w f l a g ( n o t e 1 ) 0 : t i m e r d i d n o t o v e r f l o w 1 : t i m e r h a s o v e r f l o w e d 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : d o n o t s e t b 7 b 6 n o t e : t h e t i m e r b 0 o v e r f l o w f l a g c h a n g e s t o 0 w h e n t h e c o u n t s t a r t f l a g i s 1 a n d a v a l u e i s w r i t t e n t o t h e t i m e r b 0 m o d e r e g i s t e r . t h i s f l a g c a n n o t b e s e t t o 1 b y s o f t w a r e . 0 : f i x e d t o 0 i n p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 85 rev. 1.0 figure 2.10.25 operation timing when measuring a pulse width figure 2.10.24 operation timing when measuring a pulse period count source measurement pulse count start flag timer b0 interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (indeterminate value) ? ? ? timer b0 overflow flag ? ? notes 1: counter is initialized at completion of measurement. 2: timer has overflowed. (note 1) (note 1) when measuring measurement pulse time interval from falling edge to falling edge (note 2) cleared to ??when interrupt request is accepted, or cleared by software. transfer (measured value) ? reload register counter transfer timing measurement pulse ? count source count start flag timer b0 interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (measured value) transfer (measured value) ? ? ? timer b0 overflow flag ? ? notes 1: counter is initialized at completion of measurement. 2: timer has overflowed. (note 1) (note 1) (note 1) transfer (measured value) (note 1) cleared to ??when interrupt request is accepted, or cleared by software. (note 2) transfer (indeterminate value) reload register counter transfer timing M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 86 rev. 1.0 figure 2.10.26 reserved register i (i = 0 to 2, 5) reserved register i symbol address when reset invc0 0348 16 00000000 2 invc1 0340 16 000????? 2 invc2 03a8 16 00000000 2 invc5 0376 16 00000000 2 b7 b6 b5 b4 b3 b2 b1 b0 reserved bits bit symbol bit name description rw must always be set to ? 0000000 0 figure 2.10.27 reserved register i (i = 3 and 4) reserved register i symbol address when reset invc3 0362 16 40 16 invc4 0366 16 40 16 b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name description rw reserved bits must always be set to ? 0100000 0 reserved bit must always be set to ? note: set data to this register after setting bit 2 of the protect register (address 000a 16 ) to ?.? reserved bits must always be set to ? M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 87 rev. 1.0 (4) tb0 in noise filter the input signal of pin tb0 in has the noise filter. the on/off of noise filter and selection of filter clock are set by bits 2 to 4 of the peripheral mode register. note: when using the noise filter, set bit 7 of the peripheral mode register according to the main clock frequency. figure 2.10.28 peripheral mode register p e r i p h e r a l m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t p m0 2 7 d 1 6 0 x x 0 0 0 0 0 2 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 0 0 : n o n e 0 1 : s c l 1 , s d a 1 1 0 : s c l 2 , s d a 2 1 1 : s c l 1 a n d s d a 1 , s c l 2 a n d s d a 2 b 1 b 0 n f o n b s e l 0 c l o c k s e l e c t i o n b i t s o f t b 0 i n n o i s e f i l t e r ( n o t e ) o n / o f f s e l e c t i o n b i t o f t b 0 i n p i n n o i s e f i l t e r i 2 c - b u s i n t e r f a c e p o r t s e l e c t i o n b i t s b s e l 1 w s e l 0 w s e l 1 b 3 b 2 0 0 : 0 . 2 5 m s ( r e m o v e d b u s w i d t h : m a x 0 . 7 5 m s ) 0 1 : 8 m s ( r e m o v e d b u s w i d t h : m a x 2 4 m s ) 1 0 : 1 6 m s ( r e m o v e d b u s w i d t h : m a x 4 8 m s ) 1 1 : 3 2 m s ( r e m o v e d b u s w i d t h : m a x 9 6 m s ) 0 : n o i s e f i l t e r o f f 1 : n o i s e f i l t e r o n s s c k m a i n c l o c k f r e q u e n c y s e l e c t i o n b i t 0 : f ( x i n ) = 1 0 m h z 1 : f ( x i n ) = 1 6 m h z n o t e : t h e o p e r a t i o n o f m c u i s n o t g u a r a n t e e d w h e n f ( x i n ) = 1 6 m h z . n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 88 rev. 1.0 2.11 serial i/o serial i/o is configured as 4 unites: uart0, uart2, multi-master i 2 c-bus interface 0, and multi-master i 2 c-bus interface 1. 2.11.1 uart0 and uart2 uart0 and uart2 each have an exclusive timer to generate a transfer clock, so they operate indepen- dently of each other. figure 2.11.1 shows the block diagram of uart0 and uart2. figures 2.11.2 and 2.11.3 show the block diagram of the transmit/receive unit. uarti (i = 0 and 2) has two operation modes: a clock synchronous serial i/o mode and a clock asynchronous serial i/o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 03a0 16 and 0378 16 ) determine whether uarti is used as a clock synchronous serial i/o or as a uart. although a few functions are different, uart0 and uart2 have almost the same functions. uart0 and uart2 are almost equal in their functions with minor exceptions. uart2, in particular, is compliant with the sim interface. it also has the bus collision detection function that generates an interrupt request if the txd pin and the rxd pin are different in level. table 2.11.1 shows the comparison of functions of uart0 and uart2, and figures 2.11.4 to 2.11.14 show the registers related to uarti. notes 1: only when clock synchronous serial i/o mode. 2: only when clock synchronous serial i/o mode and 8-bit uart mode. 3: only when uart mode. 4: using for sim interface. uart0 uart2 function clk polarity selection continuous receive mode selection lsb first / msb first selection impossible transfer clock output from multiple pins selection impossible impossible serial data logic switch sleep mode selection impossible impossible txd, rxd i/o polarity switch possible cmos output txd, rxd port output format n-channel open-drain output impossible parity error signal output impossible bus collision detection possible possible (note 1) possible (note 1) possible (note 1) possible (note 3) possible (note 1) possible (note 2) possible (note 1) possible (note 4) possible (note 4) table 2.11.1 comparison of functions of uart0 and uart2 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 89 rev. 1.0 figure 2.11.1 block diagram of uarti (i = 0 and 2) rxd 0 1 / (n 0 +1) 1/2 uart 0 bit rate generator (address 03a1 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 0 clock source selection f 1 f 8 f 32 reception control circuit transmission control circuit internal external txd 0 transmit/ receive unit (uart0) clk polarity reversing circuit n0 : values set to uart0 bit rate generator (brg0) n2 : values set to uart2 bit rate generator (brg2) rxd 2 reception control circuit transmission control circuit 1 / (n 2 +1) 1/16 1/16 1/2 uart2 bit rate generator (address 0379 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 2 f 1 f 8 f 32 txd 2 (uart2) rxd polarity reversing circuit txd polarity reversing circuit clk polarity reversing circuit internal external clock source selection transmit/ receive unit 1/16 1/16 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 90 rev. 1.0 figure 2.11.2 block diagram of uart0 transmit/receive unit sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txd 0 uart0 transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uart0?ransmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uart0 receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxd0 clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03a2 16 address 03a3 16 data bus low-order bits msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? data bus high-order bits M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 91 rev. 1.0 sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txd 2 uart2 transmit register par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart2?ransmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uart2 receive buffer register uart2 receive register 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxd 2 uart (8 bits) uart (9 bits) address 037e 16 address 037f 16 address 037a 16 address 037b 16 data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? reverse no reverse error signal output circuit rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp: stop bit par: parity bit figure 2.11.3 block diagram of uart2 transmit/receive unit M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 92 rev. 1.0 figure 2.11.4 uarti transmit buffer register (i = 0 and 2) b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmit data (note) nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u2tb 037b 16 , 037a 16 indeterminate w r figure 2.11.5 uarti receive buffer register (i = 0 and 2) figure 2.11.6 uarti bit rate generator (i = 0 and 2) uarti bit rate generator b7 b0 symbol address when reset u0brg 03a1 16 indeterminate u2brg 0379 16 indeterminate function assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u2rb 037f 16 , 037e 16 indeterminate b7 b0 (b15) (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found invalid invalid invalid oer fer per sum overrun error flag (note 1) framing error flag (note 1) parity error flag (note 1) error sum flag (note 1) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found nothing is assigned. in an attempt to write to these bits, write ?.?the value, if read, turns out to be ?. receive data w r receive data reserved bit must always be set to ? must always be set to ? notes 1: bits 15 through 12 are set to ??when the serial i/o mode select bit (bits 2 to 0 at addresses 03a0 16 and 0378 16 ) are set to ?00 2 ?or the receive enable bit is set to ?? (bit 15 is set to ??when bits 14 to 12 all are set to ?.? bits 14 and 13 are also set to ??when the lower byte of the uarti receive buffer register (addresses 03a6 16 and 037e 16 ) is read out. 2: the arbtration lost detecting flag is assigned to u2rb and is written only ?.?nothing is assinged to bit 11 of u0rb. this bit can neither be set nor reset, when read, he the value is ?. 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 93 rev. 1.0 uart2 transmit/receive mode register symbol address when reset u2mr 0378 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse usually set to ? 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = ? 0 : odd parity 1 : even parity invalid invalid 0 : no reverse 1 : reverse usually set to ? function (during uart mode) function (during clock synchronous serial i/o mode) uart0 transmit/receive mode register symbol address when reset u0mr 03a0 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye slep parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit sleep select bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = ? 0 : odd parity 1 : even parity invalid invalid must always be ? function (during uart mode) function (during clock synchronous serial i/o mode) figure 2.11.7 uart0 transmit/receive mode register figure 2.11.8 uart2 transmit/receive mode register M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 94 rev. 1.0 figure 2.11.9 uart0 transmit/receive control register 0 uart0 transmit/receive control register 0 symbol address when reset u0c0 03a4 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 reserved bit nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit data output select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 must always be set to ? 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be set to ? bit name bit symbol must always be set to ? 0 1 reserved bit must always be set to ? must always be set to ? must always be set to ? M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 95 rev. 1.0 figure 2.11.10 uart2 transmit/receive control register 0 n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 . u a r t 2 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 s y m b o la d d r e s sw h e n r e s e t u 2 c 00 3 7 c 1 6 0 8 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 f u n c t i o n ( d u r i n g u a r t m o d e ) w r f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) t x e p t c l k 1 c l k 0 c k p o l b r g c o u n t s o u r c e s e l e c t b i t t r a n s m i t r e g i s t e r e m p t y f l a g 0 : t r a n s m i t d a t a i s o u t p u t a t f a l l i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t r i s i n g e d g e 1 : t r a n s m i t d a t a i s o u t p u t a t r i s i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t f a l l i n g e d g e c l k p o l a r i t y s e l e c t b i t 0 0 : f 1 i s s e l e c t e d 0 1 : f 8 i s s e l e c t e d 1 0 : f 3 2 i s s e l e c t e d 1 1 : i n h i b i t e d b 1 b 0 0 : l s b f i r s t 1 : m s b f i r s t 0 : d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( d u r i n g t r a n s m i s s i o n ) 1 : n o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d ) u f o r m t r a n s f e r f o r m a t s e l e c t b i t ( n o t e 3 ) 0 0 : f 1 i s s e l e c t e d 0 1 : f 8 i s s e l e c t e d 1 0 : f 3 2 i s s e l e c t e d 1 1 : i n h i b i t e d b 1 b 0 0 : d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( d u r i n g t r a n s m i s s i o n ) 1 : n o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d ) m u s t a l w a y s b e s e t t o 0 b i t n a m e b i t s y m b o l n o t e 1 : o n l y c l o c k s y n c h r o n o u s s e r i a l i / o m o d e a n d 8 - b i t u a r t m o d e a r e v a l i d . 0 : l s b f i r s t 1 : m s b f i r s t 0 1 r e s e r v e d b i tm u s t a l w a y s b e s e t t o 0 m u s t a l w a y s b e s e t t o 0 r e s e r v e d b i tm u s t a l w a y s b e s e t t o 1 m u s t a l w a y s b e s e t t o 1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 96 rev. 1.0 figure 2.11.12 uart2 transmit/receive control register 1 u a r t 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 s y m b o l a d d r e s s w h e n r e s e t u 0 c 1 0 3 a 5 1 6 0 2 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 b i t n a m e b i t s y m b o l w r f u n c t i o n ( d u r i n g u a r t m o d e ) f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) t e t i r e r i t r a n s m i t e n a b l e b i t r e c e i v e e n a b l e b i t r e c e i v e c o m p l e t e f l a g t r a n s m i t b u f f e r e m p t y f l a g 0 : t r a n s m i s s i o n d i s a b l e d 1 : t r a n s m i s s i o n e n a b l e d 0 : d a t a p r e s e n t i n t r a n s m i t b u f f e r r e g i s t e r 1 : n o d a t a p r e s e n t i n t r a n s m i t b u f f e r r e g i s t e r 0 : r e c e p t i o n d i s a b l e d 1 : r e c e p t i o n e n a b l e d 0 : t r a n s m i s s i o n d i s a b l e d 1 : t r a n s m i s s i o n e n a b l e d 0 : d a t a p r e s e n t i n t r a n s m i t b u f f e r r e g i s t e r 1 : n o d a t a p r e s e n t i n t r a n s m i t b u f f e r r e g i s t e r 0 : r e c e p t i o n d i s a b l e d 1 : r e c e p t i o n e n a b l e d 0 : n o d a t a p r e s e n t i n r e c e i v e b u f f e r r e g i s t e r 1 : d a t a p r e s e n t i n r e c e i v e b u f f e r r e g i s t e r 0 : n o d a t a p r e s e n t i n r e c e i v e b u f f e r r e g i s t e r 1 : d a t a p r e s e n t i n r e c e i v e b u f f e r r e g i s t e r n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 . figure 2.11.11 uart0 transmit/receive control register 1 uart2 transmit/receive control register 1 symbol address when reset u2c1 037d 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register u2irs uart2 transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) u2rrm uart2 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled invalid data logic select bit 0 : no reverse 1 : reverse 0 : no reverse 1 : reverse u2lch u2ere error signal output enable bit must always be set to ? 0 : output disabled 1 : output enabled M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 97 rev. 1.0 f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) u a r t t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 2 s y m b o la d d r e s sw h e n r e s e t u c o n0 3 b 0 1 6 x 0 0 0 0 0 0 0 2 b 7b 6b 5b 4b 3b 2b 1b 0 b i t n a m e b i t s y m b o l w r f u n c t i o n ( d u r i n g u a r t m o d e ) u a r t 0 t r a n s m i t i n t e r r u p t c a u s e s e l e c t b i t r e s e r v e d b i t 0 : t r a n s m i t b u f f e r e m p t y ( t l = 1 ) 1 : t r a n s m i s s i o n c o m p l e t e d ( t x e p t = 1 ) 0 : t r a n s m i t b u f f e r e m p t y ( t l = 1 ) 1 : t r a n s m i s s i o n c o m p l e t e d ( t x e p t = 1 ) u 0 i r s m u s t a l w a y s b e s e t t o 0 0 0 0 0 0 m u s t a l w a y s b e s e t t o 0 m u s t a l w a y s b e s e t t o 0 u a r t 0 c o n t i n u o u s r e c e i v e m o d e s e l e c t b i t 0 : c o n t i n u o u s r e c e i v e m o d e d i s a b l e d 0 : c o n t i n u o u s r e c e i v e m o d e e n a b l e u 0 r r m i n v a l i d r e s e r v e d b i t s m u s t a l w a y s b e s e t t o 0 m u s t a l w a y s b e s e t t o 0 m u s t a l w a y s b e s e t t o 0 n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 . figure 2.11.14 uart2 special mode register figure 2.11.13 uart transmit/receive control register 2 u a r t 2 s p e c i a l m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t u 2 s m r0 3 7 7 1 6 0 0 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 b i t n a m e b i t s y m b o l w r f u n c t i o n ( d u r i n g u a r t m o d e ) f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) r e s e r v e d b i t s a c s e s s s 0 : o r d i n a r y 1 : f a l l i n g e d g e o f r x d 2 t r a n s m i t s t a r t c o n d i t i o n s e l e c t b i t a u t o c l e a r f u n c t i o n s e l e c t b i t o f t r a n s m i t e n a b l e b i t 0 : n o a u t o c l e a r f u n c t i o n 1 : a u t o c l e a r a t o c c u r r e n c e o f b u s c o l l i s i o n m u s t a l w a y s b e s e t t o 0 m u s t a l w a y s b e s e t t o 0 m u s t a l w a y s b e s e t t o 0 m u s t a l w a y s b e s e t t o 0 0 r e s e r v e d b i t m u s t a l w a y s b e s e t t o 0 0 0000 m u s t a l w a y s b e s e t t o 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 98 rev. 1.0 item specification transfer data format ? transfer data length: 8 bits transfer clock ? when internal clock is selected (bit 3 at addresses 03a0 16 , 0378 16 = 0) : fi/ 2(n+1) (note 1) fi = f 1 , f 8 , f 32 ? when external clock is selected (bit 3 at addresses 03a0 16 , 0378 16 = 1) : input from clki pin transmission start condition ? to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at addresses 03a5 16 , 037d 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 037d 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 037c 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 037c 16 ) = 1: clki input level = l reception start condition ? to start reception, the following requirements must be met: _ receive enable bit (bit 2 at addresses 03a5 16 , 037d 16 ) = 1 _ transmit enable bit (bit 0 at addresses 03a5 16 , 037d 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 037d 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 037c 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 037c 16 ) = 1: clki input level = l interrupt request ? when transmitting _ transmit interrupt cause select bit (bit 0 at address 03b0 16 , bit 4 at address 037d 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed _ transmit interrupt cause select bit (bit 0 at address 03b0 16 , bit 4 at address 037d 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving _ interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ? overrun error (note 2) this error occurs when the next data is ready before contents of uarti receive buffer register are read out 2.11.2 clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. tables 2.11.2 and 2.11.3 list the specifications of the clock synchronous serial i/o mode. figures 2.11.15 and 2.11.16 show the uarti transmit/receive mode register in clock synchronous serial i/o mode. generation timing table 2.11.2 specifications of clock synchronous serial i/o mode (1) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 99 rev. 1.0 item specification select function ? clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register ? switching serial data logic (uart2) whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. ? txd, rxd i/o polarity reverse (uart2) this function is reversing txd port output and rxd port input. all i/o data level is reversed. table 2.11.3 specifications of clock synchronous serial i/o mode (2) notes 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. 2: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 100 rev. 1.0 figure 2.11.15 uart0 transmit/receive mode registers in clock synchronous serial i/o mode figure 2.11.16 uart2 transmit/receive mode register in clock synchronous serial i/o mode symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit/receive mode register internal/external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode txd, rxd i/o polarity reverse bit (note) 0 : no reverse 1 : reverse note: usually set to ?? symbol address when reset u0mr 03a0 16 00 16 ckdir uart0 transmit/receive mode register internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be set to ??in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 101 rev. 1.0 table 2.11.4 lists the functions of the input/output pins during clock synchronous serial i/o mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n-channel open-drain is selected, this pin is in floating state.) table 2.11.4 input/output pin functions in clock synchronous serial i/o mode pin name function method of selection txdi (p6 3 , p7 0 ) serial data output serial data input transfer clock output transfer clock input (outputs dummy data when performing reception only) rxdi (p6 2 , p7 1 ) clki (p5 5 , p7 2 ) internal/external clock select bit (bit 3 at address 03a0 16 , 0378 16 ) = ? port p5 5 and p7 2 direction register (bit 5 at address 03eb 16 , bit 2 at address 03ef 16 ) = ? internal/external clock select bit (bit 3 at address 03a0 16 , 0378 16 ) = ? port p5 5 and p7 2 direction register (bit 5 at address 03eb 16 , bit 2 at address 03ef 16 ) = ? port p6 2 and p7 1 direction register (bits 2 at address 03ee 16 , bit 1 at address 03ef 16 )= ?? (can be used as an input port when performing transmission only) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 102 rev. 1.0 figure 2.11.17 typical transmit/receive timings in clock synchronous serial i/o mode ? example of transmit timing (when internal clock is selected) ? example of receive timing (when external clock is selected) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc stopped pulsing because transfer enable bit = ? data is set in uarti transmit buffer register tc = t clk = 2(n + 1) / fi fi: frequency of brgi count source (f 1 , f 8 , f 32 ) n: value set to brgi transfer clock transmit enable bit (te) transmit buffer empty flag (tl) clki txdi transmit register empty flag (txept) ? ? ? ? ? ? the above timing applies to the following settings: ?internal clock is selected. ?clk polarity select bit = ?? ?transmit interrupt cause select bit = ?? transmit interrupt request bit (ir) ? ? stopped pulsing because cts = ? 1 / f ext dummy data is set in uarti transmit buffer register transmit enable bit (te) transmit buffer empty flag (tl) clki rxdi receive complete flag (rl) ? ? ? ? ? ? receive enable bit (re) ? ? receive data is taken in transferred from uarti transmit buffer register to uarti transmit register read out from uarti receive buffer register the above timing applies to the following settings: ?external clock is selected. ?clk polarity select bit = ?? f ext : frequency of external clock transferred from uarti receive register to uarti receive buffer register receive interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 shown in ( ) are bit symbols. transferred from uarti transmit buffer register to uarti transmit register meet the following conditions are met when the clk input before data reception = ? ?transmit enable bit ? ?receive enable bit ? ?dummy data write to uarti transmit buffer register shown in ( ) are bit symbols. cleared to ??when interrupt request is accepted, or cleared by software cleared to ??when interrupt request is accepted, or cleared by software t clk M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 103 rev. 1.0 (1) polarity select function as shown in figure 2.11.18, the clk polarity select bit (bit 6 at addresses 03a4 16 , 037c 16 ) allows selection of the polarity of the transfer clock. ?when clk polarity select bit = ? note 2: the clk pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i clk i ?when clk polarity select bit = ? note 1: the clk pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i figure 2.11.18 polarity of transfer clock (2) lsb first/msb first select function as shown in figure 2.11.19, when the transfer format select bit (bit 7 at addresses 03a4 16 , 037c 16 ) = 0, the transfer format is lsb first; when the bit = 1, the transfer format is msb first. figure 2.11.19 transfer format lsb first ?when transfer format select bit = ? d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i ?when transfer format select bit = ? d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i msb first note: this applies when the clk polarity select bit = ?? M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 104 rev. 1.0 (3) continuous receive mode if the continuous receive mode enable bit (bits 2 at address 03b0 16 , bit 5 at address 037d 16 ) is set to 1, the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (4) serial data logic switch function (uart2) when the data logic select bit (bit6 at address 037d 16 ) = 1, and writing to transmit buffer register or reading from receive buffer register, data is reversed. figure 2.11.20 shows the example of serial data logic switch timing. figure 2.11.20 serial data logic switch timing d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd 2 (no reverse) txd 2 (reverse) h l h l h l ?when lsb first M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 105 rev. 1.0 item specification transfer data format ? character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected ? start bit: 1 bit ? parity bit: odd, even, or nothing as selected ? stop bit: 1 bit or 2 bits as selected transfer clock ? when internal clock is selected (bit 3 at addresses 03a0 16 , 0378 16 = 0) : fi/16(n+1) (note 1) fi = f 1 , f 8 , f 32 ? when external clock is selected (bit 3 at addresses 03a0 16 , 0378 16 =1) : f ext /16(n+1)(note 1) (note 2) transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 03a5 16 , 037d 16 ) = 1 - transmit buffer empty flag (bit 1 at addresses 03a5 16 , 037d 16 ) = 0 reception start condition ? to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 03a5 16 , 037d 16 ) = 1 - start bit detection interrupt request ? when transmitting generation timing - t ransmit interrupt cause select bits (bits 0 at address 03b0 16 , bit4 at address 037d 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0 at address 03b0 16 , bit4 at address 037d 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1s in parity and character bits does not match the number of 1s set ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered 2.11.3 clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 2.11.5 and 2.11.6 list the specifications of the uart mode. figure 2.11.21 and 2.11.22 show the uarti transmit/receive mode register in uart mode. table 2.11.5 specifications of uart mode (1) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 106 rev. 1.0 table 2.11.6 specifications of uart mode (2) item specification select function ? sleep mode selection (uart0) this mode is used to transfer data to and from one of multiple slave micro- computers ? serial data logic switch (uart2) this function is reversing logic value of transferring data. start bit, parity bit and stop bit are not reversed. ? txd, rxd i/o polarity switch this function is reversing txd port output and rxd port input. all i/o data level is reversed. notes 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. 2: f ext is input from the clki pin. 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 107 rev. 1.0 figure 2.11.21 uart0 transmit/receive mode register in uart mode symbol address when reset u0mr 03a0 16 00 16 ckdir uart0 transmit/receive mode register internal / external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit sleep select bit figure 2.11.22 uart2 transmit/receive mode register in uart mode symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit/receive mode register internal / external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit txd, rxd i/o polarity reverse bit (note) note: usually set to ?? M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 108 rev. 1.0 table 2.11.7 lists the functions of the input/output pins during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n- channel open-drain is selected, this pin is in floating state.) table 2.11.7 input/output pin functions in uart mode p i n n a m ef u n c t i o nm e t h o d o f s e l e c t i o n t x d i ( p 6 3 , p 7 0 ) s e r i a l d a t a o u t p u t s e r i a l d a t a i n p u t p r o g r a m m a b l e i n p u t p o r t t r a n s f e r c l o c k i n p u t r x d i ( p 6 2 , p 7 1 ) c l k i ( p 5 5 , p 7 2 ) i n t e r n a l / e x t e r n a l c l o c k s e l e c t b i t ( b i t 3 a t a d d r e s s 0 3 a 0 1 6 , 0 3 7 8 1 6 ) = 0 p o r t p 5 5 a n d p 7 2 d i r e c t i o n r e g i s t e r ( b i t 5 a t a d d r e s s 0 3 e b 1 6 , b i t 2 a t a d d r e s s 0 3 e f 1 6 ) = 0 i n t e r n a l / e x t e r n a l c l o c k s e l e c t b i t ( b i t 3 a t a d d r e s s 0 3 a 0 1 6 , 0 3 7 8 1 6 ) = 1 p o r t p 5 5 a n d p 7 2 d i r e c t i o n r e g i s t e r ( b i t 5 a t a d d r e s s 0 3 e b 1 6 , b i t 2 a t a d d r e s s 0 3 e f 1 6 ) = 0 p o r t p 6 2 a n d p 7 1 d i r e c t i o n r e g i s t e r ( b i t 2 a t a d d r e s s 0 3 e e 1 6 , b i t 1 a t a d d r e s s 0 3 e f 1 6 ) = 0 ( c a n b e u s e d a s a n i n p u t p o r t w h e n p e r f o r m i n g t r a n s m i s s i o n o n l y ) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 109 rev. 1.0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 110 rev. 1.0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 111 rev. 1.0 (2) function for switching serial data logic (uart2) when the data logic select bit (bit 6 of address 037d 16 ) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. figure 2.11.24 shows the ex- ample of timing for switching serial data logic. figure 2.11.24 timing for switching serial data logic st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txd 2 (no reverse) txd 2 (reverse) h l h l h l ? when lsb first, parity enabled, one stop bit (3) txd, rxd i/o polarity reverse function (uart2) this function is to reverse txd pin output and rxd pin input. the level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. set this function to 0 (not to reverse) for usual use. (1) sleep mode (uart0) this mode is used to transfer data between specific microcomputers among multiple microcomputers connected using uart0. the sleep mode is selected when the sleep select bit (bit 7 at address 03a0 16 ) is set to 1 during reception. in this mode, the unit performs receive operation when the msb of the received data = 1 and does not perform receive operation when the msb = 0. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 112 rev. 1.0 (4) bus collision detection function and other functions (uart2) this function is to sample the output level of the txd pin and the input level of the rxd pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. figure 2.11.26 shows the example of detection timing of a buss collision (in uart mode). and also, bit 5 of the special uart2 mode register is used as the selection bit for auto clear function select bit of enable bit. setting this bit to 1 automatically resets the transmit enable bit to 0 when 1 is set in the bus collision detection interrupt request bit (nonconformity) (refer to figure 2.11.25). bit 6 of the special uart2 mode register is used as the transmit start condition select bit. setting this bit to 1 starts the txd transmission in synchronization with the falling edge of the rxd terminal (refer to figure 2.11.26). figure 2.11.25 detection timing of a bus collision (in uart mode) figure 2.11.26 some other functions transmit start condition select bit (bit 6 of the uart2 special mode register) clk txd enabling transmission clk txd rxd with "1: falling edge of rxd 2 " selected 0: in normal state st : start bit sp : stop bit st st sp sp transfer clock txd 2 rxd 2 bus collision detection interrupt request signal ? ? ? ? ? ? ? ? bus collision detection interrupt request bit ? ? M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 113 rev. 1.0 item specification transfer data format ? transfer data 8-bit uart mode (bit 2 through bit 0 of address 0378 16 = 101 2 ) ? one stop bit (bit 4 of address 0378 16 = 0) ? with the direct format chosen set parity to even (bit 5 and bit 6 of address 0378 16 = 1 and 1 respectively) set data logic to direct (bit 6 of address 037d 16 = 0). set transfer format to lsb (bit 7 of address 037c 16 = 0). ? with the inverse format chosen set parity to odd (bit 5 and bit 6 of address 0378 16 = 0 and 1 respectively) set data logic to inverse (bit 6 of address 037d 16 = 1) set transfer format to msb (bit 7 of address 037c 16 = 1) transfer clock ? with the internal clock chosen (bit 3 of address 0378 16 = 0) : fi / 16 (n + 1) (note 1) : fi=f 1 , f 8 , f 32 ? with an external clock chosen (bit 3 of address 0378 16 = 1) : f ext / 16 (n+1) (note 1) (note 2) other settings ? the sleep mode select function is not available for uart2 ? set transmission interrupt factor to transmission completed (bit 4 of address 037d 16 = 1) transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 of address 037d 16 ) = 1 - transmit buffer empty flag (bit 1 of address 037d 16 ) = 0 reception start condition ? to start reception, the following requirements must be met: - reception enable bit (bit 2 of address 037d 16 ) = 1 - detection of a start bit interrupt request ? when transmitting generation timing when data transmission from the uart2 transfer register is completed (bit 4 of address 037d 16 = 1) ? when receiving when data transfer from the uart2 receive register to the uart2 receive buffer register is completed 2.11.4 clock-asynchronous serial i/o mode (compliant with the sim interface) the sim interface is used for connecting the microcomputer with a memory card i/c or the like; adding some extra settings in uart2 clock-asynchronous serial i/o mode allows the user to effect this function. tables 2.11.8 and 2.11.9 show the specifications of clock-asynchronous serial i/o mode (compliant with the sim interface). table 2.11.8 specifications of clock-asynchronous serial i/o mode (compliant with the sim interface) (1) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 114 rev. 1.0 item specification error detection ? overrun error (see the specifications of clock-asynchronous serial i/o) (note 3) ? framing error (see the specifications of clock-asynchronous serial i/o) ? parity error (see the specifications of clock-asynchronous serial i/o) - on the reception side, an l level is output from the txd 2 pin by use of the parity error signal output function (bit 7 of address 037d 16 = 1) when a parity error is detected - on the transmission side, a parity error is detected by the level of input to the rxd2 pin when a transmission interrupt occurs ? the error sum flag (see the specifications of clock-asynchronous serial i/o) table 2.11.9 specifications of clock-asynchronous serial i/o mode (compliant with the sim interface) (2) notes 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. 2: f ext is input from the clk 2 pin. 3: if an overrun error occurs, the uart2 receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 115 rev. 1.0 figure 2.11.27 typical transmit/receive timing in uart mode (compliant with the sim interface) transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? ? ? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p shown in ( ) are bit symbols. tc transfer clock sp stop bit data is set in uarti transmit buffer register sp a ??level returns from txd 2 due to the occurrence of a parity error. the level is detected by the interrupt routine. the level is detected by the interrupt routine. receive enable bit (re) receive complete flag (ri) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit rxd 2 the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi receive interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp shown in ( ) are bit symbols. tc transfer clock sp stop bit a ??level returns from txd 2 due to the occurrence of a parity error. txd 2 read to receive buffer read to receive buffer d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p signal conductor level (note 1) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp txd 2 rxd 2 signal conductor level (note 1) note: equal in waveform because txd 2 and rxd 2 are connected. transferred from uarti transmit buffer register to uarti transmit register cleared to ??when interrupt request is accepted, or cleared by software cleared to ??when interrupt request is accepted, or cleared by software M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 116 rev. 1.0 (1) function for outputting a parity error signal with the error signal output enable bit (bit 7 of address 037d 16 ) assigned 1, you can output an l level from the txd 2 pin when a parity error is detected. in step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. figure 2.11.28 shows the output timing of the parity error signal. figure 2.11.28 output timing of the parity error signal st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st hi-z transfer clock rxd 2 txd 2 receive complete flag h l h l h l 1 ? lsb first 0 (2) direct format/inverse format connecting the sim card allows you to switch between direct format and inverse format. if you choose the direct format, d 0 data is output from txd 2 . if you choose the inverse format, d 7 data is inverted and output from txd 2 . figure 2.11.29 shows the sim interface format. figure 2.11.29 sim interface format p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p transfer clcck txd 2 (direct) txd 2 (inverse) d7 d6 d5 d4 d3 d2 d1 d0 p figure 2.11.30 shows the example of connecting the sim interface. connect txd 2 and rxd 2 and apply pull-up. figure 2.11.30 connecting the sim interface microcomputer sim card txd 2 rxd 2 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 117 rev. 1.0 2.11.5 serial interface ports the i/o ports (p6 7 , p7 0 to p7 2 ) function as i/o ports of uart2 and multi-master i 2 c-bus interface 0 (refer to 2.11.6 multi-master i 2 c-bus interface i) . set the connection between both serial interfaces and each port by bits 0 and 1 (bsel0 and bsel1) of the peripheral mode register (address 027d 16 ) and bit 2 (fiicon) of the i 2 c0 port selection register (address 02e5 16 ). figure 2.11.31 serial interface port control uart2 rxd 2 fiicon txd 2 multi-master i 2 c-bus interface 0 scl sda ? ? bsel1 bsel0 ? scl1/rxd 2 /p7 1 ? ? scl2/clk 2 /p7 2 ? bsel1 bsel0 ? sda1/txd 2 /p7 0 ? ? sda2/p6 7 ? clk 2 ? ? ? ? ? ? ? ? M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 118 rev. 1.0 table 2.11.13 multi-master i 2 c-bus interface functions item function format in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode communication mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception scl clock frequencyn 16.1 khz to 400 khz (at bclk = 10 mhz) note : we are not responsible for any third partys infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the i 2 c control register at address 027d 16 ) for connections between the i 2 c-bus interface 0 and ports (scl1, scl2, sda1, sda2). 2.11.6 multi-master i 2 c-bus interface 0 and multi-master i 2 c-bus interface 1 the multi-master i 2 c-bus interface 0 and 1 have each dedicated circuit and operate independently. the multi-master i 2 c-bus interface i is a serial communications circuit, conforming to the philips i 2 c- bus data transfer format. this interface i, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. figures 2.11.32 and figure 2.11.33 show a block diagram of the multi-master i 2 c-bus interface i and table 2.11.13 shows multi-master i 2 c-bus interface i functions. this multi-master i 2 c-bus interface i consists of the i 2 ci address register, the i 2 ci data shift register, the i 2 ci clock control register, the i 2 ci control register, the i 2 ci status register, the i 2 ci port selection register and other control circuits. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 119 rev. 1.0 fig. 2.11.32 block diagram of multi-master i 2 c-bus interface 0 i 2 c 0 a d d r e s s r e g i s t e r ( i i c 0 s 0 d ) b 7 b 0 s a d 6 s a d 5 s a d 4 s a d 3 s a d 2 s a d 1 s a d 0 r b w n o i s e e l i m i n a t i o n c i r c u i t s e r i a l d a t a ( s d a ) a d d r e s s c o m p a r a t o r b 7 b 0 d a t a c o n t r o l c i r c u i t i 2 c 0 c l o c k c o n t r o l r e g i s t e r ( i i c 0 s 2 ) b c l k i n t e r r u p t g e n e r a t i n g c i r c u i t i n t e r r u p t r e q u e s t s i g n a l ( i i c i r q ) b 7 m s t t r x b b p i n a l a a s a d 0 l r b b 0 i 2 c 0 s t a t u s r e g i s t e r ( i i c 0 s 1 ) b 7 b 0 1 0 b i t s a d a l s b c 2 b c 1 b c 0 i 2 c 0 c o n t r o l r e g i s t e r ( i i c 0 s 1 d ) b i t c o u n t e r b b c i r c u i t c l o c k c o n t r o l c i r c u i t n o i s e e l i m i n a t i o n c i r c u i t s e r i a l c l o c k ( s c l ) b 7 b 0 a c k a c k b i t f a s t m o d e c c r 4 c c r 3 c c r 2 c c r 1 c c r 0 i n t e r n a l d a t a b u s c l o c k d i v i s i o n a l c i r c u i t e s o p 7 1 / t x d 2 / s d a 1 p 6 7 / s d a 2 0 1 b s e l 0 0 1 b s e l 1 p7 1 /rxd 2 /scl1 p 7 2 / c l k 2 / s c l 2 0 1 b s e l 0 0 1 b s e l 1 b 7 b 0 0 0 f i i c o n 0 i 2 c 0 p o r t s e l e c t i o n r e g i s t e r ( i i c 0 s 2 d ) n o t e : s e l e c t p o r t s t o u s e f o r m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e b y b i t s 0 a n d 1 ( b s e l 0 , b s e l 1 ) o f p e r i p h e r a l m o d e r e g i s t e r . 0 0 0 0 i 2 c 0 d a t a s h i f t r e g i s t e r ( i i c 0 s 0 ) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 120 rev. 1.0 fig. 2.11.33 block diagram of multi-master i 2 c-bus interface 1 i 2 c 1 a d d r e s s r e g i s t e r ( i i c 1 s 0 d ) b 7 b 0 s a d 6 s a d 5 s a d 4 s a d 3 s a d 2 s a d 1 s a d 0 r b w n o i s e e l i m i n a t i o n c i r c u i t s e r i a l d a t a ( s d a ) a d d r e s s c o m p a r a t o r b 7 i 2 c 1 d a t a s h i f t r e g i s t e r ( i i c 1 s 0 ) b 0 d a t a c o n t r o l c i r c u i t i 2 c 1 c l o c k c o n t r o l r e g i s t e r ( i i c 1 s 2 ) b c l k i n t e r r u p t g e n e r a t i n g c i r c u i t i n t e r r u p t r e q u e s t s i g n a l ( i i c i r q ) b 7 m s t t r x b b p i n a l a a s a d 0 l r b b 0 i 2 c 1 s t a t u s r e g i s t e r ( i i c 1 s 1 ) b 7 b 0 1 0 b i t s a d a l s b c 2 b c 1 b c 0 i 2 c 1 c o n t r o l r e g i s t e r ( i i c 1 s 1 d ) b i t c o u n t e r b b c i r c u i t c l o c k c o n t r o l c i r c u i t n o i s e e l i m i n a t i o n c i r c u i t s e r i a l c l o c k ( s c l ) b 7 b 0 a c k a c k b i t f a s t m o d e c c r 4 c c r 3 c c r 2 c c r 1 c c r 0 i n t e r n a l d a t a b u s c l o c k d i v i s i o n a l c i r c u i t e s o p 9 3 / d a 0 / s d a 3 p9 4 /da 1 /scl3 b 7 b 0 0 0 f i i c o n 0 i 2 c 1 p o r t s e l e c t i o n r e g i s t e r ( i i c 1 s 2 d ) 0 0 0 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 121 rev. 1.0 fig. 2.11.34 i 2 ci port selection register (i = 0, 1) (1) i 2 ci port selection register (i = 0, 1) the i 2 ci port selection register consists of bit to validate the multi-master i 2 c-bus interface i function. n bit 2: multi-master i 2 c-bus interface valid bit (fiicon) when this bit is 0, the multi-master i 2 c-bus interface i is nonactive; when 1, it is active. when selecting active, multi-master i 2 c-bus interface 0 is connected with the ports selected by bits 0 and 1 of the peripheral mode register (address 027d 16 ) and multi-master i 2 c-bus interface 1 is connected with the ports p9 3 and p9 4 . note: it needs 10-bclk cycles from setting this bit to 1 to being active of multi-master i 2 c-bus interface i. accordingly, do not access multi-master i 2 c-bus interface i-related registers in this period. i 2 ci port selection register (i = 0, 1) b7 0 b6 0 b5 0 b4 00 00 b3 b2 b1 b0 symbol address when reset iic0s2d 02e5 16 00??0000 2 iic1s2d 02ed 16 00??0000 2 rw fiicon multi-master i 2 c-bus interface valid bit 0 : nonactive 1 : active must always be set to 0 reserved bits must always be set to 0 reserved bits bit symbol bit name function M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 122 rev. 1.0 (2) i 2 ci data shift register, i 2 ci transmit buffer register (i = 0, 1) the i 2 ci data shift register is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchroniza- tion with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 ci data shift register is in a write enable status only when the eso bit of the i 2 ci control register is 1. the bit counter is reset by a write instruction to the i 2 ci data shift register. when both the eso bit and the mst bit of the i 2 ci status register are 1, the scl is output by a write instruction to the i 2 ci data shift register. reading data from the i 2 ci data shift register is always enabled regardless of the eso bit value. the i 2 ci transmit buffer register is a register to store transmit data (slave address) to the i 2 ci data shift register before restart condition generation. that is, in master, transmit data written to the i 2 ci transmit buffer register is written to the i 2 ci data shift register simultaneously. however, the scl is not output. the i 2 ci transmit buffer register can be written only when the eso bit is 1, reading data from the i 2 ci transmit buffer register is disabled regardless of the eso bit value. notes 1: to write data into the i 2 ci data shift register or the i 2 ci transmit buffer register after the mst bit value changes from 1 to 0 (slave mode), keep an interval of 20 bclk or more. 2: to generate start/restart condition after the i 2 ci data shift register or the i 2 ci transmit buffer register is written, keep an interval of 2 bclk or more. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 123 rev. 1.0 fig. 2.11.35 i 2 ci data shift register (i = 0, 1) fig. 2.11.36 i 2 ci transmit buffer register (i = 0, 1) i 2 ci data shift register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 symbol address when reset iic0s0 02e0 16 indeterminate iic1s0 02e8 16 indeterminate note: to write data into the i 2 ci data shift register after setting the mst bit to 0 (slave mode), keep an interval of 8 machine cycles or more. d0 data shift register this is an 8-bit shift register to store receive data and write transmit data. d1 d2 d3 d4 d5 d6 d7 bit symbol bit name function r w i 2 ci transmit buffer register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 symbol address when reset iic0s0s 02e6 16 indeterminate iic1s0s 02ee 16 indeterminate s0s0 transmit buffer register this is an 8-bit register to write transmit data to i 2 ci data shift register. s0s1 s0s2 s0s3 s0s4 s0s5 s0s6 s0s7 bit symbol bit name function r w M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 124 rev. 1.0 (3) i 2 ci address register (i = 0, 1) _______ the i 2 ci address register consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the start condition are detected. _______ n bit 0: read/write bit (rbw) not used when comparing addresses, in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 ci address register. the rbw bit is cleared to 0 automatically when the stop condition is detected. n bits 1 to 7: slave address (sad0Csad6) these bits store slave addresses. regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. fig. 2.11.37 i 2 ci address register (i = 0, 1) i 2 ci address register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 symbol address when reset iic0s0d 02e1 16 00 16 iic1s0d 02e9 16 00 16 rbw read/write bit M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 125 rev. 1.0 (4) i 2 ci clock control register (i = 0, 1) the i 2 ci clock control register is used to set ack control, scl mode and scl frequency. n bits 0 to 4: scl frequency control bits (ccr0Cccr4) these bits control the scl frequency. n bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to 0, the standard clock mode is set. when the bit is set to 1, the high-speed clock mode is set. n bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ] is generated. when this bit is set to 0, the ack return mode is set and sda goes to low at the occurrence of an ack clock. when the bit is set to 1, the ack non-return mode is set. the sda is held in the high status at the occurrence of an ack clock. however, when the slave address matches the address data in the reception of address data at ack bit = 0, the sda is automatically made low (ack is returned). if there is a mismatch between the slave address and the address data, the sda is automatically made high (ack is not returned). ] ack clock: clock for acknowledgement n bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowledgment response of data transmis- sion. when this bit is set to 0, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to 1, the ack clock mode is set and the master generates an ack clock upon completion of each 1-byte data transmission.the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda high) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 ci clock control register during transmission. if data is written during transmission, the i 2 ci clock generator is reset, so that data cannot be transmitted normally. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 126 rev. 1.0 fig. 2.11.38 i 2 ci clock control register (i = 0, 1) i 2 ci clock control register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 symbol address when reset iic0s2 02e4 16 00 16 iic1s2 02ec 16 00 16 ccr0 scl frequency control bits scl mode specification bit 0 : standard clock mode 1 : high-speed clock mode setup value of ccr4Cccr0 standard clock mode high speed clock mode 00 to 02 03 04 05 06 : 1d 1e 1f setup disabled setup disabled setup disabled 100 83.3 500/ccr value 17.2 16.6 16.1 setup disabled 333 250 400 (see note) 166 1000/ccr value 34.5 33.3 32.3 (at bclk = 10 mhz, unit : khz) rw ccr1 ccr2 ccr3 ccr4 fast mode ack bit 0 : ack is returned. 1 : ack is not returned. ack bit ack clock bit 0 : no ack clock 1 : ack clock ack note: at 400 khz in the high-speed clock mode, the duty is as below. 0 period : 1 period = 3 : 2 in the other cases, the duty is as below. 0 period : 1 period = 1 : 1 bit symbol bit name function M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 127 rev. 1.0 (5) i 2 ci control register (i = 0, 1) the i 2 ci control register controls the data communication format. n bits 0 to 2: bit counter (bc0Cbc2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become 000 2 and the address data is always trans- mitted and received in 8 bits. note: when the bit counter value = 111 2 , a stop condition and start condition cannot be waited. n bit 3: i 2 c-bus interface i use enable bit (eso) this bit enables usage of the multimaster i 2 c-bus interface i. when this bit is set to 0, the use disable status is provided, so the sda and the scl become high-impedance. when the bit is set to 1, use of the interface is enabled. when eso = 0, the following is performed. ? pin = 1, bb = 0 and al = 0 are set (they are bits of the i 2 ci status register). ? writing data to the i 2 ci data shift register and the i 2 ci transmit buffer register is disabled. n bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to 0, the address- ing format is selected, so that address data is recognized. when a match is found between a slave address and address data as a result of comparison or when a general call (refer to (6) i 2 ci status register, bit 1) is received, transmission processing can be performed. when this bit is set to 1, the free data format is selected, so that slave addresses are not recognized. n bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to 0, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 ci address register are compared with address data. when this bit is set to 1, the 10-bit addressing format is selected, all the bits of the i 2 ci address register are compared with address data. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 128 rev. 1.0 fig. 2.11.39 i 2 ci control register (i = 0, 1) i 2 ci control register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 symbol address when reset iic0s1d 02e3 16 00 16 iic1s1d 02eb 16 00 16 bc0 bit counter (number of transmit/receive bits) b2 b1 b0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 bc1 bc2 i 2 c-bus interface i use enable bit 0 : disabled 1 : enabled eso data format selection bit 0 : addressing format 1 : free data format als address format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format 10bit sad bit symbol bit name function r w nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 129 rev. 1.0 (6) i 2 ci status register (i = 0, 1) the i 2 ci status register controls the i 2 c-bus interface i status. bits 0 to 3, 5 are read-only bits and bits 4, 6, 7 can be read out and written to. n bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to 0. if ack is not returned, this bit is set to 1. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from 1 to 0 by executing a write instruction to the i 2 ci data shift register or the i 2 ci transmit buffer register. n bit 1: general call detecting flag (ad0) this bit is set to 1 when a general call ] whose address data is all 0 is received in the slave mode. by a general call of the master device, every slave device receives control data after the general call. the ad0 bit is set to 0 by detecting the stop condition or start condition. ] general call: the master transmits the general call address 00 16 to all slaves. n bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. < M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 130 rev. 1.0 n bit 4: i 2 c-bus interface i interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from 1 to 0. at the same time, an interrupt request signal is sent to the cpu. the pin bit is set to 0 in synchronization with a falling edge of the last clock (including the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the pin bit. when detecting the stop condition in slave, the multi-master i 2 c-bus interface interrupt request bit (ir) is set to 1 (interrupt requested) regardless of falling of pin bit. when the pin bit is 0, the scl is kept in the 0 state and clock generation is disabled. figure 2.11.41 shows an interrupt request signal generating timing chart. the pin bit is set to 1 in any one of the following conditions. ? writing 1 to the pin bit ? executing a write instruction to the i 2 ci data shift register or the i 2 ci transmit buffer register (see note). ? when the eso bit is 0 ? at reset note : it takes 8 bclk cycles or more until pin bit becomes 1 after write instructions are executed to these registers. the conditions in which the pin bit is set to 0 are shown below: ? immediately after completion of 1-byte data transmission (including when arbitration lost is detected) ? immediately after completion of 1-byte data reception ? in the slave reception mode, with als = 0 and immediately after completion of slave address or general call address reception ? in the slave reception mode, with als = 1 and immediately after completion of address data reception n bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to 0, this bus system is not busy and a start condition can be generated. when this bit is set to 1, this bus system is busy and the occurrence of a start condition is disabled by the start condition duplication prevention func- tion (see note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to 1 by detecting a start condition and set to 0 by detecting a stop condition. when the eso bit of the i 2 ci control register is 0 and at reset, the bb flag is kept in the 0 state. n bit 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides the direction of transfer for data communication. when this bit is 0, the reception mode is selected and the data of a transmitting device is received. when the bit is 1, the transmission mode is selected and address data and control data are output into the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 ci control register is 0 in the slave reception mode is selected, the trx bit ___ is set to 1 (transmit) if the least significant bit (r/w bit) of the address data transmitted by the master ___ is 1. when the als bit is 0 and the r/w bit is 0, the trx bit is cleared to 0 (receive). the trx bit is cleared to 0 in one of the following conditions. ? when arbitration lost is detected. ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication prevention function (note). ? with mst = 0 and when a start condition is detected. ? with mst = 0 and when ack non-return is detected. ? at reset M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 131 rev. 1.0 n bit 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification for data communication. when this bit is 0, the slave is specified, so that a start condition and a stop condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. when this bit is 1, the master is specified and a start condition and a stop condition are gener- ated, and also the clocks required for data communication are generated on the scl. the mst bit is cleared to 0 in one of the following conditions. ? immediately after completion of 1-byte data transmission when arbitration lost is detected ? when a stop condition is detected. ? when occurence of a start condition is disabled by the start condition duplication preventing function (see note). ? at reset note: the start condition duplication prevention function disables the following: the start condi- tion generation; bit counter reset, and scl output with the generation. this bit is valid from setting of bb flag to the completion of 1-byte transmittion/reception (occurrence of transmission/ reception interrupt request) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 132 rev. 1.0 item standard clock mode high-speed clock mode setup time 5.35 m s (53.5 cycles) 1.85 m s (18.5 cycles) hold time 4.9 m s (49 cycles) 2.4 m s (24 cycles) set/reset time for bb flag 3.75 m s (37.5 cycles) 0.85 m s (8.5 cycles) (7) start condition generation method when the eso bit of the i 2 ci control register is 1, execute a write instruction to the i 2 ci status register to set the mst, trx and bb bits to 1. a start condition will then be generated. after that, the bit counter becomes 000 2 and an scl for 1 byte is output. the start condition generation timing and bb bit set timing are different in the standard clock mode and the high-speed clock mode. refer to figure 2.11.42 for the start condition generation timing diagram, and table 2.11.13 for the start condition/stop condition generation timing table. (8) stop condition generation method when the eso bit of the i 2 ci control register is 1, execute a write instruction to the i 2 ci status register for setting the mst bit and the trx bit to 1 and the bb bit to 0. a stop condition will then be generated. the stop condition generation timing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 2.11.43 for the stop condition generation timing diagram, and table 2.11.13 for the start condition/stop condition generation timing table. fig. 2.11.42 start condition generation timing diagram fig. 2.11.43 stop condition generation timing diagram table 2.11.13 start condition/stop condition generation timing table note: absolute time at bclk = 10 mhz. the value in parentheses denotes the number of bclk cycles. i 2 c i s t a t u s r e g i s t e r w r i t e s i g n a l s e t t i m e f o r b b f l a g h o l d t i m e s e t u p t i m e s c l s d a b b f l a g i 2 c i s t a t u s r e g i s t e r w r i t e s i g n a l r e s e t t i m e f o r b b f l a g h o l d t i m e s e t u p t i m e s c l s d a b b f l a g M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 133 rev. 1.0 standard clock mode high-speed clock mode 6.5 m s (65 cycles) < scl release time 1.0 m s (10 cycles) < scl release time 3.25 m s (32.5 cycles) < setup time 0.5 m s (5 cycles) < setup time 3.25 m s (32.5 cycles) < hold time 0.5 m s (5 cycles) < hold time (9) start/stop condition detect conditions the start/stop condition detect conditions are shown in figure 2.11.44 and table 2.11.14. only when the 3 conditions of table 2.11.14 are satisfied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 134 rev. 1.0 (10) address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit ad- dressing format. the respective address communication formats is described below. n 7-bit addressing format to meet the 7-bit addressing format, set the 10bit sad bit of the i 2 ci control register to 0. the first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the i 2 ci address register. at the time of this comparison, address comparison of the rbw bit of the i 2 ci address register is not made. for the data transmission format when the 7-bit addressing format is selected, refer to figure 2.11.45, (1) and (2). n 10-bit addressing format to meet the 10-bit addressing format, set the 10bit sad bit of the i 2 ci control register to 1. an address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 ci address register. at the time of this comparison, an address ___ comparison between the rbw bit of the i 2 ci address register and the r/w bit which is the last bit of ___ the address data transmitted from the master is made. in the 10-bit addressing mode, the r/w bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. when the first-byte address data matches the slave address, the aas bit of the i 2 ci status register is set to 1. after the second-byte address data is stored into the i 2 ci data shift register, make an address comparison between the second-byte data and the slave address by software. when the address data of the 2nd bytes matches the slave address, set the rbw bit of the i 2 ci address register ___ to 1 by software. this processing can match the 7-bit slave address and r/w data, which are re- ceived after a restart condition is detected, with the value of the i 2 ci address register. for the data transmission format when the 10-bit addressing format is selected, refer to figure 2.11.45, (3) and (4). M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 135 rev. 1.0 (11) example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. set a slave address in the high-order 7 bits of the i 2 ci address register and 0 in the rbw bit. set the ack return mode and scl = 100 khz by setting 85 16 in the i 2 ci clock control register. a set 10 16 in the i 2 ci status register and hold the scl at the high. ? set a communication enable status by setting 08 16 in the i 2 ci control register. ? set the address data of the destination of transmission in the high-order 7 bits of the i 2 ci data shift register and set 0 in the least significant bit. ? set f0 16 in the i 2 ci status register to generate a start condition. at this time, an scl for 1 byte and an ack clock automatically occurs. ? set transmit data in the i 2 ci data shift register. at this time, an scl and an ack clock automatically occurs. ? when transmitting control data of more than 1 byte, repeat step ? . set d0 16 in the i 2 ci status register. after this, if ack is not returned or transmission ends, a stop condition will be generated. (12) example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode, using the addressing format, is shown below. set a slave address in the high-order 7 bits of the i 2 ci address register and 0 in the rbw bit. set the no ack clock mode and scl = 400 khz by setting 25 16 in the i 2 ci clock control register. a set 10 16 in the i 2 ci status register and hold the scl at the high. ? set a communication enable status by setting 08 16 in the i 2 ci control register. ? when a start condition is received, an address comparison is made. ? ?when all transmitted address are0 (general call): ad0 of the i 2 ci status register is set to 1and an interrupt request signal occurs. ?when the transmitted addresses match the address set in : ass of the i 2 ci status register is set to 1 and an interrupt request signal occurs. ?in the cases other than the above: ad0 and aas of the i 2 ci status register are set to 0 and no interrupt request signal occurs. ? set dummy data in the i 2 ci data shift register. ? when receiving control data of more than 1 byte, repeat step ? . when a stop condition is detected, the communication ends. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 136 rev. 1.0 (13) precautions when using multi-master i 2 c-bus interface i n bclk operation mode select the no-division mode and set the main clock frequency to f(x in ) = 10 mhz. n used instructions specify byte (.b) as data size to access multi-master i 2 c-bus interface i-related registers. n read-modify-write instruction the precautions when the read-modify-write instruction such as bset, bclr etc. is executed for each register of the multi-master i 2 c-bus interface are described below. ?i 2 ci data shift register (iicis0) when executing the read-modify-write instruction for this register during transfer, data may become a value not intended. ?i 2 ci address register (iicis0d) when the read-modify-write instruction is executed for this register at detecting the stop con- ______ dition, data may become a value not intended. it is because hardware changes the read/write bit (rbw) at the above timing. ?i 2 ci status register (iicis1) do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. ?i 2 ci control register (iicis1d) when the read-modify-write instruction is executed for this register at detecting the start condition or at completing the byte transfer, data may become a value not intended. because hardware changes the bit counter (bc0Cbc2) at the above timing. ?i 2 ci clock control register (iicis2) the read-modify-write instruction can be executed for this register. ?i 2 ci port selection register (iicis2d) since the read value of high-order 4 bits is indeterminate, the read-modify-write instruction cannot be used. ?i 2 ci transmit buffer register (iicis0s) since the value of all bits is indeterminate, the read-modify-write instruction cannot be used. fig. 2.11.45 address data communication format ss l a v e a d d r e s s a d a t aa d a t aa / a p r / w 7 b i t s 0 ? t o 8 b i t s1 t o 8 b i t s ss l a v e a d d r e s s a d a t a ad a t a ap 7 b i t s 1 ? t o 8 b i t s1 t o 8 b i t s ( 1 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r s s l a v e a d d r e s s 1 s t 7 b i t s a a d a t a 7 b i t s 0 ? b i t s1 t o 8 b i t s ( 2 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r s l a v e a d d r e s s 2 n d b y t e a d a t aa / a p 1 t o 8 b i t s s s l a v e a d d r e s s 1 s t 7 b i t s a a 7 b i t s 0 ? b i t s7 b i t s ( 3 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r w i t h a 1 0 - b i t a d d r e s s s l a v e a d d r e s s 2 n d b y t e d a t a 1 t o 8 b i t s s r s l a v e a d d r e s s 1 s t 7 b i t s a d a t a a p 1 t o 8 b i t s 1 ( 4 ) a m a s t e r - r e c e i v e r r e c e i v e s d a t a f r o m a s l a v e - t r a n s m i t t e r w i t h a 1 0 - b i t a d d r e s s s:s t a r t c o n d i t i o np : s t o p c o n d i t i o n a:a c k b i tr / w : r e a d / w r i t e b i t s r:r e s t a r t c o n d i t i o n f r o m m a s t e r t o s l a v e f r o m s l a v e t o m a s t e r r / w r / w r / w r / w M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 137 rev. 1.0 n start condition generating procedure using multi-master : fclr i (interrupt disabled) btst 5, iicis1 (bb flag confirming and branch process) jc busbusy busfree: mov.b sa, iicis0 (writing of slave address value M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 138 rev. 1.0 table 2.12.1 performance of a-d converter item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock f ad (note 2) f ad /divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) resolution 8-bit absolute precision v cc = 5v ? without sample and hold function: 5 lsb ? with sample and hold function: 5 lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 6 pins (an 0 to an 5 ) a-d conversion start condition ? software trigger a-d conversion starts when the a-d conversion start flag changes to 1 conversion speed per pin ? without sample and hold function 49 f ad cycles ? with sample and hold function 28 f ad cycles 2.12 a-d converter the a-d converter consists of one 8-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p3 6 , p3 7 , p4 0 Cp4 3 also function as the analog signal input pins. the direction registers of these pins for a-d conversion must therefore be set to input. the vref connect bit (bit 5 at address 03d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after setting bit 5 of 03d7 16 to connect v ref . the result of a-d conversion is stored in the a-d registers of the selected pins. table 2.12.1 shows the performance of the a-d converter. figure 2.12.1 shows the block diagram of the a- d converter, and figures 2.12.2 to 2.12.5 show the a-d converter-related registers. notes 1: does not depend on use of sample and hold function. 2: divide the frequency if f(x in ) exceeds 10 mhz, and make f ad frequency equal to 10 mhz. without sample and hold function, set the f ad frequency to 250khz min. with the sample and hold function, set the f ad frequency to 1mhz min. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 139 rev. 1.0 figure 2.12.1 block diagram of a-d converter 1/2 f ad 1/2 f ad a-d conversion rate selection (03c4 16 ) (03c6 16 ) (03c8 16 ) (03ca 16 ) (03cc 16 ) (03ce 16 ) cks1=1 cks0=0 a-d register 0(8) a-d register 1(8) a-d register 2(8) a-d register 3(8) a-d register 4(8) a-d register 5(8) resistor ladder successive conversion register an 0 an 1 an 3 an 4 an 5 a-d control register 0 (address 03d6 16 ) a-d control register 1 (address 03d7 16 ) v ref v in data bus high-order data bus low-order (v cc ) v ref an 2 vcut=0 v ss vcut=1 cks0=1 cks1=0 ch2,ch1,ch0=010 ch2,ch1,ch0=011 ch2,ch1,ch0=100 ch2,ch1,ch0=101 ch2,ch1,ch0=110 ch2,ch1,ch0=111 decoder comparator addresses M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 140 rev. 1.0 figure 2.12.2 a-d control register 0 figure 2.12.3 a-d control register 1 a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000??? 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : do not set 0 0 1 : do not set 0 1 0 : an 0 is selected 0 1 1 : an 1 is selected 1 0 0 : an 2 is selected 1 0 1 : an 3 is selected 1 1 0 : an 4 is selected 1 1 1 : an 5 is selected (note 2) ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 (note 2) repeat sweep mode 1 md0 md1 reserved bit must always be set to 0 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r b2 b1 b0 b4 b3 notes 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. 2: when changing a-d operation mode, set analog input pin again. 0 a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 reserved bit most always be set to ?? vcut vref connect bit a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected w r when single sweep and repeat sweep mode 0 are selected 0 0 : do not set 0 1 : an 0 and an 1 (2 pins) 1 0 : an 0 to an 3 (4 pins) 1 1 : an 0 to an 5 (6 pins) b1 b0 when repeat sweep mode 1 is selected 0 0 : do not set 0 1 : do not set 1 0 : an 0 (1 pin) 1 1 : an 0 and an 1 (2 pins) b1 b0 most always be set to ?? frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. reserved bits 00 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 141 rev. 1.0 figure 2.12.5 a-d register i (i = 0 to 5) figure 2.12.4 a-d control register 2 a-d register i symbol address when reset adi(i=0 to 5) 03c4 16 , 03c6 16 , 03c8 16 indeterminate 03ca 16 , 03cc 16 , 03ce 16 indeterminate eight bits of a-d conversion result function r w b7 b0 a-d control register 2 (note) symbol address when reset adcon2 03d4 16 0000???0 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function r w note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. nothing is assigned. in an attempt to write to these bits, write ?.? the value, if read, turns out to be ?. smp reserved bits must always be set to ? 000 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 142 rev. 1.0 table 2.12.2 one-shot mode specifications item specification function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-d conversion start flag stop condition ? end of a-d conversion ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin one of an 0 to an 5 , as selected reading of result of a-d converter read a-d register corresponding to selected pin 2.12.1 one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conver- sion. table 2.12.2 shows the specifications of one-shot mode. figures 2.12.6 and 2.12.7 show the a-d control register in one-shot mode. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 143 rev. 1.0 figure 2.12.6 a-d control register 0 in one-shot mode figure 2.12.7 a-d control register 1 in one-shot mode a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000??? 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0: f ad /4 is selected 1: f ad /2 is selected cks0 w r 0 0 0 0 0 : do not set 0 0 1 : do not set 0 1 0 : an 0 is selected 0 1 1 : an 1 is selected 1 0 0 : an 2 is selected 1 0 1 : an 3 is selected 1 1 0 : an 4 is selected 1 1 1 : an 5 is selected b2 b1 b0 0 0 : one-shot mode b4 b3 ch0 notes 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. 2: when changing a-d operation mode, it is necessary to set analog input pins again. reserved bit must always be set to ? 0 (note 2) (note 2) a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 reserved bit must always be set to ? vcut reserved bits vref connect bit a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : vref connected must always be set to ? w r invalid in one-shot mode 0 1 frequency select bit1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. 00 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 144 rev. 1.0 table 2.12.3 repeat mode specifications item specification function the pin selected by the analog input pin select bit is used for repeated a-d conversion star condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of an 0 to an 5 , as selected reading of result of a-d converter read a-d register corresponding to selected pin 2.12.2 repeat mode in repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conversion. table 2.12.3 shows the specifications of repeat mode. figures 2.12.8 and 2.12.9 show the a-d control register in repeat mode. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 145 rev. 1.0 figure 2.12.8 a-d conversion register 0 in repeat mode a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000??? 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r 01 0 0 0 : do not set 0 0 1 : do not set 0 1 0 : an 0 is selected 0 1 1 : an 1 is selected 1 0 0 : an 2 is selected 1 0 1 : an 3 is selected 1 1 0 : an 4 is selected 1 1 1 : an 5 is selected b2 b1 b0 0 1 : repeat mode b4 b3 reserved bit must always be set to ? 0 notes 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. 2: when changing a-d operation mode, it is necessary to set analog input pins again. (note 2) (note 2) figure 2.12.9 a-d conversion register 1 in repeat mode a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 reserved bit most always be set to ? vcut reserved bits vref connect bit a-d operation mode select bit 1 1 : vref connected w r invalid in repeat mode 0 most always be set to ? 1 frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 0 : any mode other than repeat sweep mode 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. 00 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 146 rev. 1.0 2.12.3 single sweep mode in single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a-d conversion. table 2.12.4 shows the specifications of single sweep mode. figures 2.12.10 and 2.12.11 show the a-d control register in single sweep mode. table 2.12.4 single sweep mode specifications item specification function the pins selected by the a-d sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d converter start flag stop condition ? end of a-d conversion ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins) reading of result of a-d converter read a-d register corresponding to selected pin M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 147 rev. 1.0 figure 2.12.10 a-d control register 0 in single sweep mode a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000??? 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 0 : single sweep mode md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r 1 0 invalid in single sweep mode b4 b3 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. reserved bit must always be set to ? 0 figure 2.12.11 a-d control register 1 in single sweep mode a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 reserved bit must always be set to ? vcut reserved bits vref connect bit 0 : any mode other than repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 0 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. when single sweep and repeat sweep mode 0 are selected 0 0 : do not set 0 1 : an 0 and an 1 (2 pins) 1 0 : an 0 to an 3 (4 pins) 1 1 : an 0 to an 5 (6 pins) b1 b0 must always be set to ? 1 frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 00 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 148 rev. 1.0 item specification function the pins selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) table 2.12.5 repeat sweep mode 0 specifications 2.12.4 repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. table 2.12.5 shows the specifications of repeat sweep mode 0. figures 2.12.12 and 2.12.13 show the a-d control register in repeat sweep mode 0. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 149 rev. 1.0 figure 2.12.12 a-d control register 0 in repeat sweep mode 0 a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000??? 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r 1 1 invalid in repeat sweep mode 0 b4 b3 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. reserved bit must always be set to ? 0 figure 2.12.13 a-d control register 1 in repeat sweep mode 0 a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 vcut reserved bits vref connect bit 0 : any mode other than repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 0 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. when single sweep and repeat sweep mode 0 are selected 0 0 : do not set 0 1 : an 0 and an 1 (2 pins) 1 0 : an 0 to an 3 (4 pins) 1 1 : an 0 to an 5 (6 pins) b1 b0 must always be set to ? 1 frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 00 reserved bit must always be set to ? 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 150 rev. 1.0 2.12.5 repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins selected using the a-d sweep pin select bit. table 2.12.6 shows the specifications of repeat sweep mode 1. figures 2.12.14 and 2.12.15 show the a-d control register in repeat sweep mode 1. table 2.12.6 repeat sweep mode 1 specifications item specification function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit example : an 0 selected an 0 an 1 an 0 an 2 an 0 an 3 , etc start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 (1 pin), an 0 and an 1 (2 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) figure 2.12.14 a-d control register 0 in repeat sweep mode 1 a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000??? 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 1 md0 md1 reserved bit adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r 1 1 invalid in repeat sweep mode 1 b4 b3 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. must always be set to ? 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 151 rev. 1.0 figure 2.12.15 a-d control register 1 in repeat sweep mode 1 a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 vcut vref connect bit 1 : repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 1 note : if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. when repeat sweep mode 1 is selected 0 0 : do not set 0 1 : do not set 1 0 : an 0 (1 pin) 1 1 : an 0 and an 1 (2 pins) b1 b0 1 frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 reserved bits must always be set to ? 00 reserved bit must always be set to ? 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 152 rev. 1.0 2.12.6 sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 03d4 16 ) to 1. when sample and hold is selected, the rate of conversion of each pin increases. as a result, a 28 f ad cycle is achieved. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 153 rev. 1.0 figure 2.13.1 block diagram of d-a converter 2.13 d-a converter this is an 8-bit, r-2r type d-a converter. the microcomputer contains two independent d-a converters of this type. d-a conversion is performed when a value is written to the corresponding d-a register. bits 0 and 1 (d-a output enable bits) of the d-a control register decide if the result of conversion is to be output. do not set the target port to output mode if d-a conversion is to be performed. output analog voltage (v) is determined by a set value (n : decimal) in the d-a register. v = v ref x n/ 256 (n = 0 to 255) v ref : reference voltage table 2.13.1 lists the performance of the d-a converter. figure 2.13.1 shows the block diagram of the d-a converter. figure 2.13.2 shows the a-d control register, figure 2.13.3 shows the d-a register and figure 2.13.4 shows the d-a converter equivalent circuit. table 2.13.1 performance of d-a converter item performance conversion method r-2r method resolution 8 bits analog output pin 2 channels p9 3 /da 0 p9 4 /da 1 data bus low-order bits d-a register0 (8) r-2r resistor ladder d-a0 output enable bit d-a register1 (8) r-2r resistor ladder d-a1 output enable bit (address 03d8 16 ) (address 03da 16 ) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 154 rev. 1.0 v cc (v ref ) v ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r da0 msb lsb d-a0 output enable bit "0" "1" d-a0 register0 note 1: the above diagram shows an instance in which the d-a register is assigned 2a 16 . 2: the same circuit as this is also used for d-a1. 3: to reduce the current consumption when the d-a converter is not used, set the d-a output enable bit to 0 and set the d-a regis ter to 00 16 so that no current flows in the resistors rs and 2rs. d-a register i (i = 0, 1) symbol address when reset dai (i = 0,1) 03d8 16 , 03da 16 indeterminate w r b7 b0 function r w output value of d-a conversion figure 2.13.2 d-a control register d-a control register symbol address when reset dacon 03dc 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a0 output enable bit da0e bit symbol bit name function r w 0 : output disabled 1 : output enabled d-a1 output enable bit 0 : output disabled 1 : output enabled da1e nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. figure 2.13.3 d-a register i (i = 0 and 1) figure 2.13.4 d-a converter equivalent circuit M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 155 rev. 1.0 2.14 data slicer this microcomputer includes the data slicer function for the closed caption decoder (referred to as the ccd). this function takes out the caption data superimposed in the vertical blanking interval of a composite video signal. a composite video signal which makes the sync chips polarity negative is input to the cv in pin. when the data slicer function is not used, the data slicer circuit and the timing signal generating circuit can be cut off by setting bit 0 of the data slicer control register 1 (address 0260 16 ) to 0. these settings can realize the low-power dissipation. note: when using the data slicer, set bit 7 of the peripheral mode register (address 027d 16 ) according to the main clock frequency. figure 2.14.1 data slicer block diagram composite video signal 1 m w data slicer control register 2 (address 0261 16 ) data slicer control register 1 (address 0260 16 ) clock run-in detect register (address 0269 16 ) caption position register (address 0266 16 ) data clock position register (address 026a 16 ) interrupt request generating circuit data slicer interrupt request synchronizing signal counter synchronizing separation circuit sync slice circuit clamping circuit low-pass filter timing signal generating circuit clock run-in determination circuit data slice line specification circuit start bit detecting circuit data clock generating circuit 16-bit shift register caption data register 1 (addresses 0263 16 , 0262 16 ) data bus comparator 0.1 m f 470 w 560 pf cv in 1 m f 1 k w 200 pf h sync hlf + reference voltage generating circuit v hold 1000 pf data slicer on/off caption data register 2 (addresses 0265 16 , 0264 16 ) external circuit note : make the length of wiring which is connected to v hold , hlf, and cv in pin as short as possible so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 156 rev. 1.0 figure 2.14.2 termination of data slicer input/output pins when data slicer circuit and timing generating circuit is in off state figure 2.14.3 termination of data slicer input/output pins when timing signal generating circuit is in on state M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 157 rev. 1.0 figures 2.14.4 and 2.14.5 the data slicer control registers. figure 2.14.4 data slicer control register 1 figure 2.14.5 data slicer control register 2 b7 b6 b5 b4 b3 b2 b1 b0 data slicer control register 1 00 reserved bits 000 definition of fields 1 (f1) and 2 (f2) h sep v sep f1: h sep v sep f2: r w bit name function must always be set to ? symbol address when reset dsc1 0260 16 00 16 bit symbol dsc10 dsc11 dsc12 reference clock source selection bit data slicer and timing signal generating circuit control bit 0: f2 1: f1 selection bit of data slice reference voltage generating field 0: stopped 1: operating 0: video signal 1: h sync signal b7 b6 b5 b4 b3 b2 b1 b0 r w data slicer control register 2 00 0: data is not latched yet and a clock-run-in is not determined. 1: data is latched and a clock-run-in is determined. caption data latch completion flag 1 reserved bit read-only test bit 0: f2 1: f1 field determination flag 0: method (1) 1: method (2) vertical synchronous signal (v sep ) generating method selection bit 0: match 1: mismatch v-pulse shape determination flag function bit name definition of fields 1 (f1) and 2 (f2) h sep v sep f1: h sep v sep f2: bit symbol dsc20 dsc23 dsc24 dsc25 symbol address when reset dsc2 0261 16 ?0?0??0? 2 must always be set to ? reserved bit must always be set to ? read-only test bit M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 158 rev. 1.0 2.14.2 clamping circuit and low-pass filter the clamp circuit clamps the sync chip part of the composite video signal input from the cv in pin. the low- pass filter attenuates the noise of clamped composite video signal. the cv in pin to which composite video signal is input requires a capacitor (0.1 mf) coupling outside. pull down the cv in pin with a resistor of hundreds of kiloohms to 1 m w . in addition, we recommend to install externally a simple low-pass filter using a resistor and a capacitor at the cv in pin (refer to figure 2.14.1). 2.14.3 sync slice circuit this circuit takes out a composite sync signal from the output signal of the low-pass filter. 2.14.4 synchronous signal separation circuit this circuit separates a horizontal synchronous signal and a vertical synchronous signal from the compos- ite sync signal taken out in the sync slice circuit. (1) horizontal synchronous signal (h sep ) a one-shot horizontal synchronizing signal hsep is generated at the falling edge of the composite sync signal. (2) vertical synchronous signal (v sep ) as a vsep signal generating method, it is possible to select one of the following 2 methods by using bit 4 of the data slicer control register 2 (address 0261 16 ). ?method 1 the l level width of the composite sync signal is measured. if this width exceeds a certain time, a v sep signal is generated in synchronization with the rising of the timing signal immediately after this l level. ?method 2 the l level width of the composite sync signal is measured. if this width exceeds a certain time, it is detected whether a falling of the composite sync signal exits or not in the l level period of the timing signal immediately after this l level. if a falling exists, a v sep signal is generated in synchronization with the rising of the timing signal (refer to figure 2.14.6). figure 2.14.6 shows a v sep generating timing. the timing signal shown in the figure is generated from the reference clock which the timing generating circuit outputs. reading bit 5 of data slicer control register 2 permits determinating the shape of the v-pulse portion of the composite sync signal. as shown in figure 2.14.7, when the a level matches the b level, this bit is 0. in the case of a mismatch, the bit is 1. figure 2.14.6 v sep generating timing (method 2) composite s timing signal v sep signal measure ??period a v sep signal is generated at a rising of the timing signal immediately after the ??level width of the composite sync signal exceeds a certain time. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 159 rev. 1.0 2.14.5 timing signal generating circuit this circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. it also generates various timing signals on the basis of the reference clock, horizontal syn- chronous signal and vertical synchronizing signal. the circuit operates by setting bit 0 of data slicer control register 1 (address 0260 16 ) to 1. the reference clock can be used as a display clock for osd function in addition to the data slicer. the h sync signal can be used as a count source instead of the composite sync signal. however, when the h sync signal is selected, the data slicer cannot be used. a count source of the reference clock can be selected by bit 2 of data slicer control register 1 (address 0260 16 ). for the pins hlf, connect a resistor and a capacitor as shown in figure 2.14.1 make the length of wiring which is connected to these pins as short as possible so that a leakage current may not be generated. note: it takes a few tens of milliseconds until the reference clock becomes stable after the data slicer and the timing signal generating circuit are started. in this period, various timing signals, h sep signals and v sep signals become unstable. for this reason, take stabilization time into consideration when programming. figure 2.14.7 determination of v-pulse waveform composite sync signal a b 0 1 1 bit 5 of dsc2 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 160 rev. 1.0 2.14.6 data slice line specification circuit (1) specification of data slice line this circuit decides a line on which caption data is superimposed. the line 21 (fixed), 1 appropriate line for a period of 1 field (total 2 line for a period of 1 field), and both fields (f1 and f2) are sliced their data. the caption position register (address 0266 16 ) is used for each setting (refer to table 2.14.1). the counter is reset at the falling edge of v sep and is incremented by 1 every hsep pulse. when the counter value matched the value specified by bits 4 to 0 of the caption position register, this h sep is sliced. the values of 00 16 to 1f 16 can be set in the caption position register (at setting only 1 appropriate line). figure 2.14.8 shows the signals in the vertical blanking interval. figure 2.14.9 shows the caption position register. (2) specification of line to set slice voltage the reference voltage for slicing (slice voltage) is generated for the clock run-in pulse in the particular line (refer to table 2.14.1). the field to generate slice voltage is specified by bit 1 of data slicer control register 1. the line to generate slice voltage 1 field is specified by bits 6, 7 of the caption position register (refer to table 2.14.1). (3) field determination the field determination flag can be read out by bit 3 of data slicer control register 2. this flag change at the falling edge of v sep . figure 2.14.8 signals in vertical blanking interval video signal vertical blanking interval composite video signal count value to be set in the caption position register (?f 16 ?in this case) h sep v sep h sep magnified drawing clock run-in start bit + 16-bit data start bit window for deteminating clock-run-in composite video signal line 21 1 appropriate line is set by the caption position register (when setting line 19) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 161 rev. 1.0 figure 2.14.9 caption position register field and line to generate slice voltage ? field specified by bit 1 of dsc1 ? line 21 (total 1 line) ? field specified by bit 1 of dsc1 ? a line specified by bits 4 to 0 of cps (total 1 line) (see note 3) ? field specified by bit 1 of dsc1 ? line 21 (total 1 line) ? field specified by bit 1 of dsc1 ? line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) field and line to be sliced data ? both fields of f1 and f2 ? line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) ? both fields of f1 and f2 ? a line specified by bits 4 to 0 of cps (total 1 line) (see note 3) ? both fields of f1 and f2 ? line 21 (total 1 line) ? both fields of f1 and f2 ? line 21 and a line specified by bits 4 to 0 of cps (total 2 lines) (see note 2) cps b7 0 0 1 1 b6 0 1 0 1 notes 1: dsc is data slicer control register 1. cps is caption position register. 2: set 00 16 to 10 16 to bits 4 to 0 of cps. 3: set 00 16 to 1f 16 to bits 4 to 0 of cps. table 2.14.1 specification of data slice line b7 b6 b5 b4 b3 b2 b1 b0 caption position register caption position bits function bit name r w bit symbol cps0 symbol address when reset cps 0266 16 00?00000 2 refer to the corresponding table (table 2.14.1). slice line mode specification bits (in 1 field) 0: data is not latched yet and a clock-run-in is not determined. 1: data is latched and a clock-run-in is determined. caption data latch completion flag 2 cps5 cps6 cps7 cps1 cps2 cps3 cps4 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 162 rev. 1.0 2.14.7 reference voltage generating circuit and comparator the composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. (1) reference voltage generating circuit this circuit generates a reference voltage (slice voltage) by using the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit. connect a capacitor between the v hold pin and the v ss pin, and make the length of wiring as short as possible so that a leakage current may not be generated. (2) comparator the comparator compares the voltage of the composite video signal with the voltage (reference volt- age) generated in the reference voltage generating circuit, and converts the composite video signal into a digital value. 2.14.8 start bit detecting circuit this circuit detects a start bit at line decided in the data slice line specification circuit. the detection of a start bit is described below. ? a sampling clock is generated by dividing the reference clock output by the timing signal. ? a clock run-in pulse is detected by the sampling clock. ? after detection of the pulse, a start bit pattern is detected from the comparator output. 2.14.9 clock run-in determination circuit this circuit determinates clock run-in by counting the number of pulses in a window of the composite video signal. the reference clock count value in one pulse cycle is stored in bits 3 to 7 of the clock run-in detect register (address 0269 16 ). read out these bits after the occurrence of a data slicer interrupt (refer to 2.14.12 interrupt request generating circuit). figure 2.14.10 shows the structure of clock run-in detect register. figure 2.14.10 clock run-in detect register b7 b6 b5 b4 b3 b2 b1 b0 r w clock run-in detect register test bits number of reference clocks to be counted in one clock run-in pulse period. clock run-in detection bits read-only function bit name bit symbol crd3 symbol address when reset crd 0269 16 00 16 crd4 crd5 crd6 crd7 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 163 rev. 1.0 2.14.10 data clock generating circuit this circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. the data clock stores caption data to the 16-bit shift register. when the 16-bit data has been stored and the clock run-in determination circuit determines clock run-in, the caption data latch completion flag is set. this flag is reset at a falling of the vertical synchronous signal (v sep ). figure 2.14.11 data clock position register b7 b6 b5 b4 b3 b2 b1 b0 data clock position register data clock position set bits nothing is assigned. if an attempt to write to these bits, write ?.?the read turns out to be ?. function bit name r w bit symbol dps0 symbol address when reset dps 026a 16 xxx00001 2 dps1 dps2 dps3 dps4 2.14.11 16-bit shift register the caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. the contents of the stored caption data can be obtained by reading out the caption data register 1 (addresses 0263 16 , 0262 16 ) and caption data register 2 (addresses 0265 16 , 0264 16 ). these registers are reset to 0 at a falling of v sep . read out data registers 1 and 2 after the occurrence of a data slicer interrupt (refer to 2.14.12 interrupt request generating circuit). M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 164 rev. 1.0 2.14.12 interrupt request generating circuit the interrupt requests as shown in table 2.14.3 are generated by combination of the following bits; bits 6 and 7 of the caption position register (address 0266 16 ). read out the contents of data registers 1, 2 and the contents of bits 3 to 7 of the clock run-in detect register after the occurrence of a data slicer interrupt request. slice line specification mode cps completion flag 1 (bit 0 of dsc2) completion flag 2 (bit 5 of cps) caption data register 1 caption data register 2 line 21 a line specified by bits 4 to 0 of cps line 21 line 21 a line specified by bits 4 to 0 of cps invalid invalid a line specified by bits 4 to 0 of cps 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of cps 16-bit data of line 21 16-bit data of line 21 16-bit data of a line specified by bits 4 to 0 of cps invalid invalid 16-bit data of a line specified by bits 4 to 0 of cps contents of caption data latch completion flag contents of 16-bit shift register bit 7 0 0 1 1 bit 6 0 1 0 1 cps: caption position register dsc2: data slicer control register 2 table 2.14.2 contents of caption data latch completion flag and 16-bit shift register cps occurrence sources of interrupt request at end of data slice line after slicing line 21 after a line specified by bits 4 to 0 of cps after slicing line 21 after slicing line 21 b7 0 1 b6 0 1 0 1 table 2.14.3 occurrence sources of interrupt request cps: caption position register figure 2.14.12 data slicer reserved register i (i = 1, 2) data slicer reserved register i (i =1, 2) symbol address when reset dr1 0268 16 00 16 dr2 0267 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 reserved bit s bit symbol bit name description rw mest always be set to ? 000 0 0 00 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 165 rev. 1.0 figure 2.15.1 h sync counter register 2.15 h sync counter the synchronous signal counter counts h sync from h sync count input pins (hc0/p7 5 , hc1/p7 7 ) as a count source. the count value in a certain time (t time; 1024 m s, 2048 m s, 4096 m s and 8192 m s) divided system clock f 32 is stored into the 8-bit latch. accordingly, the latch value changes in the cycle of t time. when the count value exceeds ff 16 , ff 16 is stored into the latch. the latch value can be obtained by reading out the h sync counter latch (address 027f 16 ). a count source and count update cycle (t time) are selected by bits 0, 3 and 4 of the h sync counter register. figure 2.15.1 shows the h sync counter and figure 2.15.2 shows the synchronous signal counter block diagram. note: when using the h sync counter, set the port direction register corresponding to the h sync count input pins for input. figure 2.15.2 h sync counter block diagram b7 b6 b5 b4 b3 b2 b1 b0 r w h sync counter register count source switch bit input polarity switch bit function bit name nothing is assigned. in an attempt to write to this bit, write ?.? the value, if read, turns out to be ?. count freguency selection bits b4 b3 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 166 rev. 1.0 2.16 osd functions table 2.16.1 outlines the osd functions of this microcomputer. this osd function can display the follow- ing: the block display (32 characters 5 16 lines or 42 characters 5 16 lines) and the sprite display, and can display the both display at the same time. there are 3 display modes and they are selected by a block unit. the display modes are selected by block control register i (i = 1 to 16). the features of each display are described below. note: when using osd function, select no-division mode as bclk operating mode and set the main clock frequency to f(x in ) = 10 mhz. table 2.16.1 features of each display style c c m o d e ( c l o s e d c a p t i o n m o d e ) o s d m o d e ( o n - s c r e e n d i s p l a y m o d e ) o s d s m o d e d i s p l a y s t y l e p a r a m e t e r n u m b e r o f d i s p l a y c h a r a c t e r s 3 2 c h a r a c t e r s 5 1 6 l i n e s / 4 2 c h a r a c t e r s 5 1 6 l i n e s 1 6 5 2 0 d o t s ( c h a r a c t e r d i s p l a y a r e a : 1 6 5 2 6 d o t s ) 4 k i n d s 5 1 , 5 2 1 t c 5 1 / 2 h , 1 t c 5 1 h s m o o t h i t a l i c , u n d e r l i n e , f l a s h 1 s c r e e n : 8 k i n d s ( a c h a r a c t e r u n i t ) m a x . 5 1 2 k i n d s p o s s i b l e ( a c h a r a c t e r u n i t , 1 s c r e e n : 4 k i n d s , m a x . 5 1 2 k i n d s ) l a y e r 1 a n a l o g r , g , b o u t p u t ( e a c h 8 a d j u s t m e n t l e v e l s : 5 1 2 c o l o r s ) , d i g i t a l o u t 1 , o u t 2 o u t p u t d o t s t r u c t u r e k i n d s o f c h a r a c t e r r o m o s d l e n a b l e m o d e o s d l d i s a b l e m o d e 2 5 4 k i n d s 5 0 8 k i n d s 2 5 4 k i n d s k i n d s o f c h a r a c t e r s i z e s ( s e e n o t e 1 ) p r e - d i v i d e r a t i o ( n o t e ) d o t s i z e a t t r i b u t e c h a r a c t e r f o n t c o l o r i n g c h a r a c t e r b a c k g r o u n d c o l o r i n g d i s p l a y l a y e r o s d o u t p u t ( s e e n o t e 2 ) p o s s i b l e ( a s c r e e n u n i t , m a x 5 1 2 k i n d s ) r a s t e r c o l o r i n g a u t o s o l i d s p a c e f u n c t i o n o t h e r f u n c t i o n ( s e e n o t e 3 ) t r i p l e l a y e r o s d f u n c t i o n , w i n d o w f u n c t i o n , b l a n k f u n c t i o n p o s s i b l e d i s p l a y e x p a n s i o n ( m u l t i l i n e d i s p l a y ) 1 4 k i n d s 1 t c 5 1 / 2 h , 1 t c 5 1 h , 1 . 5 t c 5 1 / 2 h , 1 . 5 t c 5 1 h , 2 t c 5 2 h , 3 t c 5 3 h b o r d e r p o s s i b l e ( a c h a r a c t e r u n i t , 1 s c r e e n : 1 6 k i n d s , m a x . 5 1 2 k i n d s ) 1 s c r e e n : 1 6 k i n d s ( a c h a r a c t e r u n i t ) m a x . 5 1 2 k i n d s n o t e s 1 : t h e c h a r a c t e r s i z e i s s p e c i f i e d w i t h d o t s i z e a n d p r e - d i v i d e r a t i o ( r e f e r t o 2 . 1 6 . 3 d o t s i z e ) . 2: a s f o r s p r i t e d i s p l a y , o u t 2 i s n o t o u t p u t . 3: a s f o r s p r i t e d i s p l a y , t h e w i n d o w f u n c t i o n d o e s n o t o p e r a t e . 4: t h e d i v i d e r a t i o o f t h e f r e q u e n c y d i v i d e r ( t h e p r e - d i v i d e c i r c u i t ) i s r e f e r r e d a s p r e - d i v i d e r a t i o h e r e a f t e r . b l o c k d i s p l a y o s d l m o d e c d o s d m o d e ( c o l o r d o t o n - s c r e e n d i s p l a y m o d e ) s p r i t e d i s p l a y 5 1 , 5 2 , 5 3 l a y e rs 1 , 2 2 4 5 3 2 d o t s 2 5 4 k i n d s 1 2 k i n d s l a y e r 3 ( w i t h h i g h e s t p r i o r i t y ) 1 6 5 2 6 d o t s 1 2 6 k i n d s 1 4 k i n d s 1 t c 5 1 / 2 h , 1 t c 5 1 h , 1 . 5 t c 5 1 / 2 h , 1 . 5 t c 5 1 h , 2 t c 5 2 h , 3 t c 5 3 h 1 s c r e e n : 1 6 k i n d s ( a d o t u n i t ) ( o n l y s p e c i f i e d d o t s a r e c o l o r e d b y a c h a r a c t e r u n i t ) m a x . 5 1 2 k i n d s 1 s c r e e n : 1 6 k i n d s ( a d o t u n i t ) m a x . 5 1 2 k i n d s 3 2 5 2 0 d o t s 2 k i n d s o f r a m f o n t 8 k i n d s 1 t c 5 1 / 2 h , 1 t c 5 1 h , 2 t c 5 2 h , 3 t c 5 3 h 1 c h a r a c t e r 5 2 l i n e s 5 1 , 5 2 o s d p m o d e 1 6 5 2 0 d o t s 1 2 5 2 0 d o t s 8 5 2 0 d o t s 4 5 2 0 d o t s 1 t c 5 1 / 2 h , 1 t c 5 1 h , 2 t c 5 2 h , 3 t c 5 3 h l a y e r 1l a y e rs 1 , 2 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 167 rev. 1.0 the osd circuit has an extended display mode. this mode allows multiple lines (16 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. figure 2.16.1 shows the display-enable fonts for each display style. figure 2.16.2 shows the block diagram of the osd circuit. figure 2.16.3 shows the osd control register 1. figure 2.16.4 shows the block control register i. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 168 rev. 1.0 figure 2.16.1 display-enable fonts for each display style 20 dots 16 dots 26 dots 16 dots 32 dots 24 dots display styles display-enable fonts cc mode osds mode osdp mode osdl mode cdosd mode sprite blank area blank area underline area 20 dots 16 dots 20 dots 12 dots 4 dots 8 dots 20 dots 20 dots ***** * : only character codes ** : blank font 20 dots 32 dots 26 dots M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 169 rev. 1.0 figure 2.16.2 block diagram of osd circuit osd ram (see note 1) 19 bits 5 32 characters 5 16 lines data bus osd rom (character font) (see note 2) 16 dots 5 20 dots 5 254 characters 24 dots 5 32 dots 5 254 characters output circuit r g b out1 out2 control register for osd sprite osd control register osd control register 1 osd control register 2 horizontal position register clock control register i/o polarity control register osd control register 3 raster color register top border control register bottom border control register block control register i vertical position register i color palette register i osd reserved register i osd control register 4 left border control register right border control register sprite vertical position register i sprite horizontal position register (address 0201 16 ) (address 0202 16 ) (address 0203 16 ) (address 0204 16 ) (address 0205 16 ) (address 0206 16 ) (address 0207 16 ) (addresses 0209 16 , 0208 16 ) (addresses 020d 16 , 020c 16 ) (addresses 020f 16 , 020e 16 ) (addresses 0210 16 to 021f 16 ) (addresses 0220 16 to 023f 16 ) (addresses 0240 16 to 025b 16 ) (addresses 025d 16 to 027a 16 , 027b 16 to 027c 16 ) (address 025f 16 ) (addresses 0271 16 , 0270 16 ) (addresses 0273 16 , 0272 16 ) (addresses 0274 16 to 0277 16 ) (addresses 0279 16 , 0278 16 ) display oscillation circuit osc1 osc2 h sync v sync data slicer clock clock for osd osd control circuit osd rom (color dot font) 16 dots 5 26 dots 5 4 planes 5 94 characters osd ram (sprite) 32 dots 5 20 dots 5 4 planes 5 2 lines shift register notes 1: in 42 character-mode, 19 bits 5 42 characters 5 16 lines 2: in osdl disable mode, 16 dots 5 20 dots 5 762 characters. shift register shift register shift register M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 170 rev. 1.0 figure 2.16.3 osd control register 1 b7 b6 b5 b4 b3 b2 b1 b0 bit name r w osd control register 1 osd control bit scan mode selection bit automatic solid space control bit border type selection bit flash mode selection bit layer mixing control bits vertical window/blank control bit function 0 : all-blocks and sprite display off 1 : all-blocks and sprite display on 0 : normal scan mode 1 : bi-scan mode 0 : all bordered 1 : shadow bordered (see note 2) 0 : color signal of character background part does not flash 1 : color signal of character background part flashes 0 0: logic sum (or) of layer 1? color and layer 2? color 0 1: layer 1? color has priority 1 0: layer 2? color has priority 1 1: do not set. b7 b6 0 : off 1 : on 0 : off 1 : on notes 1 : even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next v sync . 2: shadow border is output at right and bottom side of the font. 3: out2 is always ored, regardless of values of these bits. bit symbol oc16 oc15 oc14 oc13 oc12 oc11 oc10 symbol address when reset oc1 0202 16 00 16 (see note 1) oc17 (see note 3) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 171 rev. 1.0 figure 2.16.4 block control register i (i = 0 to 16) b 7 b 6 b 5 b 4 b 3 b 2 b1 b 0 block control register i display mode selection bits dot size selection bits pre-divide ratio selection bits b0 b1 b0 functions 0 0 0 display off 0 0 1 osds mode (no bordered) 0 1 0 cc mode 0 1 1 cdosd mode 1 0 0 osdp mode (no bordered) 1 0 1 osds mode (bordered) 1 1 0 osdp mode (bordered) 1 1 1 osdl mode bit name function r w notes 1: tc is osd clock cycle divided in pre-divide circuit 2: h is h sync 3: this character size is available only in layer 2. at this time, set layer 1? pre-divide ratio = 5 2, layer 1? horizontal dot size = 1tc. 4: in osdl and osdp modes, 1.5tc size cannot be used. b6 b5 b4 b3 pre-divide dot size ratio 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 1 1 5 1 5 2 5 3 1tc 5 1/2h 1tc 5 1h 2tc 5 2h 3tc 5 3h 1tc 5 1/2h 1tc 5 1h 2tc 5 2h 3tc 5 3h 1.5tc 5 1/2h (see notes 3, 4) 1.5tc 5 1h (see notes 3, 4) 1tc 5 1/2h 1tc 5 1h 2tc 5 2h 3tc 5 3h 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 nothing is assigned. in an attempt to write to this bit, write ?.? the value, if read, turns out to be indeterminate. bit symbol bci_0 bci_3 bci_5 bci_1 bci_2 bci_4 bci_6 symbol bci (i = 1 to 16) address 0210 16 to 021f 16 when reset indeterminate M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 172 rev. 1.0 display mode pre-divide ratio dot size horizontal display start position vertical display start position 2.16.1 triple layer osd three built-in layers of display screens accommodate triple display of channels, volume, etc., closed caption, and sprite displays within layers 1 to 3. the layer to be displayed in each block is selected by bit 0 or 1 of the osd control register 2 for each display mode (refer to figure 2.16.7). layer 3 always displays the sprite display. when the layer 1 block and the layer 2 block overlay, the screen is composed with layer mixing by bit 6 or 7 of the osd control register 1, as shown in figure 2.16.5. layer 3 always takes display priority of layers 1 and 2. notes 1: when mixing layer 1 and layer 2, note table 2.16.2. 2: osdp mode is always displayed on layer 1. and also, it cannot be overlapped with layer 2s block. 3: out2 is always ored, regardless of values of bits 6, 7 of the osd control register 1. and besides, even when out2 (layer 1 and layer 2) overlaps with sprite display (layer 3), out2 is output without masking. cc, osds/l, cdosd mode 5 1, 5 2 (cc mode) 5 1 to 5 3 (osd, cdosd mode) 1t c 5 1/2h, 1t c 5 1h (cc mode) 1t c 5 1h, 1t c 5 1/2h, 2t c 5 2h, 3t c 5 3h (osds/l, cdosd mode) arbitrary table 2.16.2 mixing layer 1 and layer 2 note: in the osdl mode, 1.5t c size cannot be used. block in layer 1 block in layer 2 block parameter osds/l, cdosd mode same as layer 1 (see note) pre-divide ratio = 5 1 pre-divide ratio = 5 2 1t c 5 1/2h 1t c 5 1/2h, 1.5t c 5 1/2h 1t c 5 1h 1t c 5 1h, 1.5t c 5 1h (see note) ? same size as layer 1 ?1.5t c can be selected only when: layer 1s pre-divide ratio = 5 2 and layer 1s horizontal dot size = 1t c . as this time, vertical dot size is the same as layer 1. same position as layer 1 arbitrary however, when dot size is 2tc 5 2h or 2tc 5 3h, set difference between vertical display position of layer 1 and that of layer 2 as follows. ?2tc 5 2h: 2h units ?3tc 5 3h: 3h units fig 2.16.5 triple layer osd layer 2 layer 1 block 1 block 2 block 7 block 8 ... layer 3 block 9 block 15 block 10 block 16 ... sprite r, g, b of layer 1/layer 2 out2 of layer 1/layer 2 note : when layer 1/layer 2 and sprite display overlay each other, only out2 in layer 1/layer 2 is output. sprite layer 1/layer 2 sprite (except transparent) a' a M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 173 rev. 1.0 figure 2.16.6 display example of triple layer osd figure 2.16.7 osd control register 2 b7 b1 b0 layer 1 layer 2 0 0 cc, osds/l/p, cdosd 0 1 cc, osds/l/p cdosd 1 0 cc, osdp, cdosd osds/l 1 1 cc, osdp cdosd osds/l b6 b5 b4 b3 b2 b1 b0 bit name function r w osd control register 2 r, g, b signal output selection bit window/blank selection bit 1 (horizontal) solid space output bit 0: out1 output 1: out2 output 0: digital output 1: analog output (8 gradations) horizontal window/blank control bit 0: off 1: on 0: horizontal blank function 1: horizontal window function window/blank selection bit 2 (vertical) 0: vertical blank function 1: vertical window function osd interrupt request selection bit 0: at completion of layer 1 block display 1: at completion of layer 2 block display display layer selection bits bit symbol oc20 oc22 oc23 oc24 oc25 oc26 oc27 symbol address when reset oc2 0203 16 00 16 oc21 display example of layer 1 = ?ello,?layer 2 = ?h5 ch5 hello logical sum (or) of layer 1? color and layer 2? color (see note) oc17 = ?,?oc16 = ? layer 1? color has priority oc17 = ?? oc16 = ? ch5 hello layer 2? color has priority oc17 = ?,?oc16 = ? hello ch5 note: the logical sum (or) of layer mixing is not or of the color palette registers?contents (color), but that of color pallet registers?numbers (i). example) when the logical sum (or) is performed on the color palettes 1 and 4; the number 1 (0001 2 ) and number 4 (0100 2 ) are ored and it results in the number 5 (0101 2 ). that is, the contents (color) of color palette register 5 is output. the color of color palette register 5 is output in the ored part, regardless of colors of color palettes registers 1 and 4. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 174 rev. 1.0 2.16.2 display position the display positions of characters are specified by a block. there are 16 blocks, blocks 1 to 16. up to 32 characters (32-character mode)/42 characters (42-character mode)/ can be displayed in each block (re- fer to 2.16.6 memory for osd). the display position of each block can be set in both horizontal and vertical directions by software. the display position in the horizontal direction can be selected for all blocks in common from 256-step display positions in units of 4 t osc (t osc = osd oscillation cycle). the display position in the vertical direction for each block can be selected from 1024-step display posi- tions in units of 1 t h ( t h = h sync cycle). blocks are displayed in conformance with the following rules: ? when the display position is overlapped with another block in the dame layer (figure 2.16.8 (b)), a lower block number (1 to 16) is displayed on the front. ? when another block display position appears while one block is displayed in the dame layer (figure 2.16.8 (c)), the block with a larger set value as the vertical display start position is displayed. however, do not display block with the dot size of 2t c 5 2h or 3t c 5 3h during display period ( ] ) of another block. ] in the case of osds/p mode block: 20 dots in vertical from the vertical display start position. ] in the case of osdl mode block: 32 dots in vertical from the vertical display start position. ] in the case of cc or cdosd mode block: 26 dots in vertical from the vertical display start position. figure 2.16.8 display position hp vp2 block 1 block 2 (a) example when each block is separated vp3 block 3 hp vp1 = vp2 block 1 (b) example when block 2 overlaps with block 1 (block 2 is not displayed) hp vp1 vp2 (c) example when block 2 overlaps in process of block 1 block 1 block 2 note: vpi (i = 1 to 16) indicates the vertical display start position of display block i. vp1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 175 rev. 1.0 the display position in the vertical direction is determined by counting the horizontal sync signal (h sync ). at this time, when v sync and h sync are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of h sync signal from after fixed cycle of rising edge (falling edge) of v sync signal. so interval from rising edge (falling edge) of v sync signal to rising edge (falling edge) of h sync signal needs enough time (2 5 bclk cycles or more) for avoiding jitter. the polarity of h sync and v sync signals can select with the i/o polarity control register (address 0206 16 ). figure 2.16.9 supplement explanation for display position when bits 0 and 1 of the i/o polarity control register (address 0206 16 ) are set to ??(negative polarity) v sync signal input v sync control signal in microcomputer 0.1 to 0.2 [ m s] ( bclk = 10 mhz ) period of counting h sync si g nal (note 2) h sync si g nal input not count 12345 notes 1 : the vertical position is determined by counting falling edge of h sync signal after rising edge of v sync control signal in the microcomputer. 2: do not generate falling edge of h sync signal near rising edge of v sync control signal in microcomputer to avoid jitter. 3: the pulse width of h sync needs 26 5 bclk cycles or more (bclk = 10 mhz). 8 5 bclk c y cles or more 26 5 bclk cycles or more M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 176 rev. 1.0 the vertical position for each block can be set in 1024 steps (where each step is 1t h (t h : h sync cycle)) as values 002 16 to 3ff 16 in vertical position register i (i = 1 to 16) (addresses 0220 16 to 023f 16 ). the vertical position register i is shown in figure 2.16.10. figure 2.16.10 vertical position register i (i = 1 to 16) vertical position register i b7 b6 b5 b4 b3 b2 b1 b0 (b15) b7 (b8) b0 b6 b5 b4 b3 b2 b1 symbol address when reset vpi (i = 1 to 16) even addresses within addresses 0220 16 to 023f 16 , indeterminate odd addresses within addresses 0220 16 to 023f 16 bit symbol vpi_9 to vpi_0 vertical display start position control bits of sprite font bit name function r w vertical display start position = t h 5 n (n: setting value, t h : h sync cycle) nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. note : do not set vpi 001 16 , vpi 3 400 16 . figure 2.16.11 horizontal position register horizontal position register b7 b6 b5 b4 b3 b2 b1 b0 symbol address when reset hp 0204 16 00 16 bit symbol hp_7 to hp_0 horizontal display start position control bits bit name function r w horizontal display start position = 4t osc 5 n (n: setting value, t osc : osd oscillation cycle) note : the setting value synchronizes with the v sync . the horizontal position is common to all blocks, and can be set in 256 steps (where 1 step is 4t osc , t osc being osd oscillation cycle) as values 00 16 to ff 16 in bits 0 to 7 of the horizontal position register (address 0204 16 ). the horizontal position register is shown in figure 2.16.11. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 177 rev. 1.0 note : 1t c (t c : osd clock cycle divided in pre-divide circuit) gap occurs between the horizontal display start position set by the horizontal position register and the most left dot of the 1st block. accord- ingly, when 2 blocks have different pre-divide ratios, their horizontal display start position will not match. ordinary, this gap is 1t c regardless of character sizes, however, the gap is 1.5t c only when the character size is 1.5t c . figure 2.16.12 notes on horizontal display start position h sync 1t c 1t c block 1 (pre-divide ratio = 1) 1t c 4t osc 5 n note 1 block 2 (pre-divide ratio = 2) block 3 (pre-divide ratio = 3) block 4 (pre-divide ratio = 2, character size = 1.5tc) 1.5t c = value of horizontal position register (decimal notation) = osd clock cycle divided in pre-divide circuit = osd oscillation cycle = 50tosc n tc tosc tdef t def M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 178 rev. 1.0 2.16.3 dot size the dot size can be selected by a block unit. the dot size in vertical direction is determined by dividing h sync in the vertical dot size control circuit. the dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the osd clock source (data slicer clock, osc1, main clock) in the pre-divide circuit. the clock cycle divided in the pre-divide circuit is defined as 1t c . the dot size is specified by bits 3 to 6 of the block control register. refer to figure 2.16.4 (the block control register i), refer to figure 2.16.15 (the clock control register). the block diagram of dot size control circuit is shown in figure 2.16.13. notes 1 : the pre-divide ratio = 3 cannot be used in the cc mode. 2 : the pre-divide ratio of the layer 2 must be same as that of the layer 1 by the block control register i. 3 : in the bi-scan mode, the dot size in the vertical direction is 2 times as compared with the normal mode. refer to 2.16.18 scan mode about the scan mode. figure 2.16.13 block diagram of dot size control circuit figure 2.16.14 definition of dot sizes h sync synchronous circuit cycle 5 2 cycle 5 3 pre-divide circuit clock cycle = 1t c horizontal dot size control circuit vertical dot size control circuit osd control circuit data slice r cloc k (see note) osc1 note: to use data slicer clock, set bit 0 of data slicer control register 1 to ?. 1 dot scanning line of f1 (f2) scanning line of f2 (f1) 1/2h 1h 2h 3h 3t c 2t c 1t c 1t c in normal scan mode M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 179 rev. 1.0 2.16.4 clock for osd as a clock for display to be used for osd, it is possible to select one of the following 3 types. ? data slicer clock output from the data slicer (approximately 26 mhz) ? clock from the lc oscillator supplied from the pins osc1 and osc2 ? clock from the ceramic resonator (or the quartz-crystal oscillator) from the pins osc1 and osc2 figure 2.16.15 clock control register figure 2.16.16 block diagram of osd selection circuit clock selection bit 0: data slicer clock 1: osc1 clock osc1 oscillating mode selection bits 0 0: stopped 0 1: do not set. 1 0: lc oscillating mode 1 1: ceramic ?quartz-crystal oscillating mode b2 b1 b7 b6 b5 b4 b3 b2 b1 b0 bit name function clock control register bit symbol symbol address when reset cs 0205 16 00 16 r w cs0 cs1 000 cs2 reserved bits must always be set to ? 0 0 data slicer circuit data slicer clock osc1 clock lc c eramic quartz-crystal o scillating mode f or os d cs2 , cs1 osd control circuit cs0 (see note) note : to use data slicer clock, set bit 0 of data slicer control register 1 to ?. 10 11 0 1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 180 rev. 1.0 2.16.5 field determination display to display the block with vertical dot size of 1/2h, whether an even field or an odd field is determined through differences in a synchronizing signal waveform of interlacing system. the dot line 0 or 1 (refer to figure 2.16.18) corresponding to the field is displayed alternately. in the following, the field determination standard for the case where both the horizontal sync signal and the vertical sync signal are negative-polarity inputs will be explained. a field determination is determined by detecting the time from a falling edge of the horizontal sync signal until a falling edge of the v sync control signal (refer to figure 2.16.9) in the microcomputer and then comparing this time with the time of the previous field. when the time is longer than the comparing time, it is regarded as even field. when the time is shorter, it is regarded as odd field. the field determination flag changes at a rising edge of v sync control signal in the microcomputer . the contents of this field can be read out by the field determination flag (bit 7 of the i/o polarity control register at address 0206 16 ). a dot line is specified by bit 6 of the i/o polarity control register (refer to figure 2.16.18). however, the field determination flag read out from the cpu is fixed to 0 at even field or 1 at odd field, regardless of bit 6. figure 2.16.17 i/o polarity control register i/o polarity control register h sync input polarity switch bit 0 : positive polarity input 1 : negative polarity input 0 : positive polarity input 1 : negative polarity input r, g, b output polarity switch bit 0 : positive polarity output 1 : negative polarity output v sync input polarity switch bit r w note: refer to figure 2.16.19. 0 : ? ?at even field ??at odd field 1 : ? ?at even field ??at odd field out1 output polarity switch bit 0 : positive polarity output 1 : negative polarity output out2 output polarity switch bit 0 : positive polarity output 1 : negative polarity output display dot line selection bit (see note) field determination flag 0 : even field 1 : odd field b7 b6 b5 b4 b3 b2 b1 b0 symbol pc bit symbol bit name function address 0206 16 when reset 1000x000 2 pc0 pc1 pc2 pc4 pc5 pc6 pc7 must always be set to ?. reserved bit 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 181 rev. 1.0 figure 2.16.18 relation between field determination flag and display font both h sync signal and v sync signal are negative-polarity input field even odd field determination flag(note) display dot line selection bit display dot line 0 (t2 > t1) 1 (t3 < t2) 0 1 0 1 when using the field determination flag, set bit 7 of the peripheral mode register (address 027d 16 ) according to the main clock frequency. t2 t3 osd rom font configuration diagram dot line 0 dot line 1 odd dot line 0 dot line 1 (n - 1) field (odd-numbered) t1 0.5 to 0.1 [ms] at f(bclk) = 10 mhz cc mode ?cdosd mode 1 35 79111315 1 3 5 7 9 11 13 15 17 19 21 23 25 26 24 22 20 18 16 14 12 10 8 6 4 2 24 6810121416 1 3 5 7 9 11 13 15 17 19 20 18 16 14 12 10 8 6 4 2 13579111315 2 4 6 8 10 12 14 16 osds mode h sync v sync and v sync control signal in microcom- puter upper : v sync signal lower : v sync control signal in micro- computer (n) field (even-numbered) (n + 1) field (odd-numbered) when the display dot line selection bit is ?, the ? ?font is displayed at even field, the ??font is displayed at odd field. bit 7 of the i/o polarity control register can be read as the field determination flag : ??is read at odd field, ??is read at even field. note : the field determination flag changes at a rising edge of the v sync control signal (negative-polarity input) in the microcomputer. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 182 rev. 1.0 2.16.6 memory for osd there are 2 types of memory for osd : osd rom (addresses 90000 16 to affff 16 ) used to store character dot data and osd ram (addresses 0400 16 to 13ff 16 ) used to specify the kinds of display characters, display colors, and sprite display. the following describes each type of memory. (1) rom for osd (addresses 90000 16 to affff 16 ) the dot pattern data for osd characters is stored in the character font area in the osd rom and the cd font data for osd characters is stored in the color dot font area in the osd rom. to specify the kinds of the character font and the cd font, it is necessary to write the character code into the osd ram. for character font, there are the following 2 mode. ? osdl enable mode 16 5 20-dot font and 24 5 32-dot font ? osdl disable mode 16 5 20-dot font the modes are selected by bit 3 of the osd control register 3 for each screen. the character font data storing address for osdl enable/osdl disable mode are shown in figures 2.16.20 and 2.16.21. the conditions for each osdl enable/disable mode are shown in figure 2.16.22. the cd font data storing address is shown in figure 2.16.23. figure 2.16.19 osd control register 4 osd control register 4 symbol address when reset oc4 025f 16 xxxxx00 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function oc40 oc41 osdl mode se l ec ti o n b it number of horizontal display characters selection bit 0 : osdl enable mode 1 : os dl d i sab l e m ode 0 : 32 characters for each block (32-character mode) 1 : 42 characters for each block (42-character mode) nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 183 rev. 1.0 figure 2.16.20 character font data storing address (osdl enable mode) line number (1) 02 16 09 16 03 16 04 16 05 16 06 16 07 16 08 16 11 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 15 16 12 16 13 16 14 16 area 0 area 1 b 0 b7 b 0 b7 0a 16 02 16 09 16 03 16 04 16 05 16 06 16 07 16 08 16 11 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 15 16 12 16 13 16 14 16 area 0 area 1 b 0 b7 b 0 b7 0a 16 17 16 16 16 1b 16 18 16 19 16 1a 16 1e 16 1c 16 1d 16 1f 16 area 2 b 0 b7 00 16 01 16 osd rom address of character font data (osdl enable mode) ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 osd rom address bit 0 line number (1) (msb to lsb) character code (c7 to c0) area bit character code (c8)=0 0 0 line number (2) (msb to lsb) character code (c7 to c0) area bit character code (c8)=1 0 line number (2) (msb to lsb) character code (c6 to c0) 0 00 kinds of font areas 0, 1 area 2 structure of address pointer character code (c7) line number (2) 1 font (1) character codes 000 16 to 0ff 16 line number (1) = ?2 16 ?to ?5 16 line number (2) = ?0 16 ?to ?f 16 character code = ?00 16 ?to ?ff 16 ?(?fe 16 ,??ff 16 ,??00 16 ?and ?80 16 ?cannot be used. write ?f 16 ?to corresponding addresses.) area bit = 0: area 0 1: area 1 font (1) (character codes 000 16 to 0ff 16 ) font (2) (character codes 100 16 to 1ff 16 ) font (2) character codes 100 16 to 1ff 16 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 184 rev. 1.0 figure 2.16.21 character font data storing address (osdl disable mode) font (1) font (2) (character codes 000 16 to 27f 16 ) line number (1) 02 16 09 16 03 16 04 16 05 16 06 16 07 16 08 16 11 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 15 16 12 16 13 16 14 16 area 0 area 1 b 0 b7 b 0 b7 0a 16 09 16 06 16 07 16 08 16 17 16 0b 16 0c 16 0d 16 0e 16 0f 16 16 16 1b 16 18 16 19 16 1a 16 area 0 area 1 b 0 b7 b 0 b7 0a 16 1f 16 1c 16 1d 16 1e 16 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 osd rom address bit font (1) character codes 000 16 to 1ff 16 line number (1) (msb to lsb) character code (c8 to c0) area bit character code (c9)=0 0 line number (1) (msb to lsb) character code (c8 to c0) area bit character code (c9)=1 0 line number (3) (nl3 to nl0) character code (c6 to c0) 0 kinds of font structure of address pointer 0 area bit font (2) character codes 200 16 to 27f 16 font (3) character codes 280 16 to 2ff 16 1 line number (2) line number (3) (nl4) osd rom address of character font data (osdl disable mode) line number (1) = ?2 16 ?to ?5 16 line number (3) = ?6 16 ?to ?f 16 ?and ?6 16 ?to ?f 16 character code = ?00 16 ?to ?ff 16 ?(?fe 16 ,??ff 16 ,??00 16 ,??80 16 ,??00 16 ?and ?80 16 ?cannot be used. write ?f 16 ?to corresponding addresses.) area bit = 0: area 0 1: area 1 font (3) ( character codes 280 16 to 2ff 16 ) 1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 185 rev. 1.0 figure 2.16.22 conditions for each osdl enable/disable mode osdl enable/ disable mode display mode & character code osdl enable mode (bit 0 of osd control register 4 = ?? display mode cc osds/p osdl cc osds/p osdl specified character code display off depending on the relationship of osdl enable/disable mode, display mode and character code, note the conditions below. 300 16 to 3ff 16 osdl disable mode (bit 0 of osd control register 4 = ?? 280 16 to 2ff 16 200 16 to 27f 16 100 16 to 1ff 16 000 16 to 0ff 16 used used (see note 1) used used not used (see note 3) not used (see note 3) not used (see note 3) used used used used display off used display off used (no border ) (see note 2) display off not used display off notes 1: part of 24 5 32 font is displayed. 24 32 16 24 32 16 20 2: in osdl disable mode, character codes ?80 16 ?to ?ff 16 ?are used in osds/p mode (no border). 3: as setting this make output of font data indeterminate, do not use. however, ?fe 16 ?and ?ff 16 ?can be used as character codes of blank font output in osdp mode. used (see note 1) character size l s character size s M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 186 rev. 1.0 figure 2.16.23 color dot font data storing address 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 osd rom address of cd font data line number cd code area bit = ?0 16 ?to ?9 16 = ?0 16 ?to ?f 16 ?(?f 16 ?and ?0 16 ?can not be used. write ?f 16 ?to the corresponding address.) = 0 : area 0 1 : area 1 09 16 05 16 06 16 07 16 08 16 0a 16 11 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 15 16 12 16 13 16 14 16 plane 2 (color palette selection bit 2) plane 1 (color palette selection bit 1) plane 0 (color palette selection bit 0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 plane 3 (color palette selection bit 3) ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 osd rom address bit line number/ cd code/area bit 1 line number (msb to lsb) cd code (c5 to c0) area bit plane selection bit 1 cd code (c6) display example line number 02 16 09 16 03 16 04 16 05 16 06 16 07 16 08 16 0a 16 11 16 0b 16 0c 16 0d 16 0e 16 0f 16 10 16 15 16 12 16 13 16 14 16 area 0 area 1 b 0 b7 b 0 b7 19 16 16 16 17 16 18 16 00 16 01 16 02 16 03 16 04 16 b 0 b7 b0 b7 19 16 16 16 17 16 18 16 00 16 01 16 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 2 22 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 11 11 3 3 11 11 3 3 3 3 3 line number area 0 area 1 color palette set by rc13 to rc16 of osd ram is selected color palette 1 is selected color palette 2 is selected color palette 3 is selected color palette 4 is selected 0 1 2 3 4 color palette 11 is selected 11 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 187 rev. 1.0 (2) osd ram (osd ram for character, addresses 0400 16 to 0eff 16 ) the osd ram for character is allocated at addresses 0400 16 to 0eff 16 , and is divided into a display character code specification part, color code 1 specification part, and color code 2 specification part for each block. the number of characters for 1 block (32- or 42-character mode) is selected by bit 1 of the osd control register 4. tables 2.16.3 to 2.16.7 show the address map. for example, to display 1 character position (the left edge) in block 1, write the character code in address 0400 16 , write color code 1 at 0401 16 , and write color code 2 at 0480 16 . the structure of the osd ram is shown in figure 2.16.25. note : for blocks of the following dot sizes, the 3nth (n = 1 to 14) character is skipped as compared with ordinary block. n in osdl mode: all dot size. n in osds and cdosd modes of layer 2: 1.5tc 5 1/2h or 1.5tc 5 1h accordingly, maximum 22 characters (32-character mode)/28 characters (42-character mode) are only displayed in 1 block. blocks with dot size of 1t c 5 1/2h and 1t c 5 1h, or blocks on the layer 1. the ram data for the 3nth character does not effect the display. any character data can be stored here. and also, note the following only in 32-character mode. as the character is displayed in the 28ths character area in 42-character mode, set ordinarily. ? in osds mode the character is not displayed, and only the left 1/3 part of the 22nd character back ground is displayed in the 22nds character area. when not displaying this back- ground, set transparent for character background color. ? in osdl mode set a blank character or a character of transparent color to the 22nd character. ? in cdosd mode the character is not displayed, and color palette color specified by bits 3 to 6 of color code 1 can be output in the 22nds character area (left 1/3 part). figure 2.16.24 ram data for 3rd character (in 32-character mode) 1 1 2 2 3 4 4 5 5 7 6 8 7 10 8 11 9 13 10 14 11 16 12 17 13 19 14 20 15 22 16 23 17 25 18 26 19 28 20 29 21 31 22 32 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829303132 display sequence ram address order display sequence ram address order ?1tc size block ?1.5tc size block ?osdl block M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 188 rev. 1.0 display position (from left) 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character block block 1 block 2 block 3 block 4 block 5 block 6 block 7 block 8 block 9 block 10 color code 1 specification 0401 16 0403 16 : 043d 16 043f 16 0441 16 0443 16 : 047d 16 047f 16 0501 16 0503 16 : 053d 16 053f 16 0541 16 0543 16 : 057d 16 057f 16 0601 16 0603 16 : 063d 16 063f 16 0641 16 0643 16 : 067d 16 067f 16 0701 16 0703 16 : 073d 16 073f 16 0741 16 0743 16 : 077d 16 077f 16 0801 16 0803 16 : 083d 16 083f 16 0841 16 0843 16 : 087d 16 087f 16 color code 2 specification 0480 16 0482 16 : 04bc 16 04be 16 04c0 16 04c2 16 : 04fc 16 04fe 16 0580 16 0582 16 : 05bc 16 05be 16 05c0 16 05c2 16 : 05fc 16 05fe 16 0680 16 0682 16 : 06bc 16 06be 16 06c0 16 06c2 16 : 06fc 16 06fe 16 0780 16 0782 16 : 07bc 16 07be 16 07c0 16 07c2 16 : 07fc 16 07fe 16 0880 16 0882 16 : 08bc 16 08be 16 08c0 16 08c2 16 : 08fc 16 08fe 16 character code specification 0400 16 0402 16 : 043c 16 043e 16 0440 16 0442 16 : 047c 16 047e 16 0500 16 0502 16 : 053c 16 053e 16 0540 16 0542 16 : 057c 16 057e 16 0600 16 0602 16 : 063c 16 063e 16 0640 16 0642 16 : 067c 16 067e 16 0700 16 0702 16 : 073c 16 073e 16 0740 16 0742 16 : 077c 16 077e 16 0800 16 0802 16 : 083c 16 083e 16 0840 16 0842 16 : 087c 16 087e 16 table 2.16.3 contents of osd ram (1st to 32nd character) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 189 rev. 1.0 block block 11 block 12 block 13 block 14 block 15 block 16 color code 1 specification 0901 16 0903 16 : 093d 16 093f 16 0941 16 0943 16 : 097d 16 097f 16 0a01 16 0a03 16 : 0a3d 16 0a3f 16 0a41 16 0a43 16 : 0a7d 16 0a7f 16 0b01 16 0b03 16 : 0b3d 16 0b3f 16 0b41 16 0b43 16 : 0b7d 16 0b7f 16 color code 2 specification 0980 16 0982 16 : 09bc 16 09be 16 09c0 16 09c2 16 : 09fc 16 09fe 16 0a80 16 0a82 16 : 0abc 16 0abe 16 0ac0 16 0ac2 16 : 0afc 16 0afe 16 0b80 16 0b82 16 : 0bbc 16 0bbe 16 0bc0 16 0bc2 16 : 0bf0 16 0bfe 16 character code specification 0900 16 0902 16 : 093c 16 093e 16 0940 16 0942 16 : 097c 16 097e 16 0a00 16 0a02 16 : 0a3c 16 0a3e 16 0a40 16 0a42 16 : 0a7c 16 0a7e 16 0b00 16 0b02 16 : 0b3c 16 0b3e 16 0b40 16 0b42 16 : 0b7c 16 0b7e 16 table 2.16.4 contents of osd ram (1st to 32nd character) (continued) display position (from left) 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character 1st character 2nd character : 31st character 32nd character M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 190 rev. 1.0 table 2.16.5 contents of osd ram (33rd to 42nd character) display position (from left) 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character block block 1 block 2 block 3 block 4 block 5 block 6 block 7 color code 1 specification 0c01 16 0c03 16 : 0c0d 16 0c0f 16 0e01 16 0e03 16 0c11 16 0c13 16 : 0c1d 16 0c1f 16 0e09 16 0e0b 16 0c21 16 0c23 16 : 0c2d 16 0c2f 16 0e11 16 0e13 16 0c31 16 0c33 16 : 0c3d 16 0c3f 16 0e19 16 0e1b 16 0c41 16 0c43 16 : 0c4d 16 0c4f 16 0e21 16 0e23 16 0c51 16 0c53 16 : 0c5d 16 0c5f 16 0e29 16 0e2b 16 0c61 16 0c63 16 : 0c6d 16 0c6f 16 0e31 16 0e33 16 color code 2 specification 0c80 16 0c82 16 : 0c8c 16 0c8e 16 0e80 16 0e82 16 0c90 16 0c92 16 : 0c9c 16 0c9e 16 0e88 16 0e8a 16 0ca0 16 0ca2 16 : 0cac 16 0cae 16 0e90 16 0e92 16 0cb0 16 0cb2 16 : 0cbc 16 0cbe 16 0e98 16 0e9a 16 0cc0 16 0cc2 16 : 0ccc 16 0cce 16 0ea0 16 0ea2 16 0cd0 16 0cd2 16 : 0cdc 16 0cde 16 0ea8 16 0eaa 16 0ce0 16 0ce2 16 : 0cec 16 0cee 16 0eb0 16 0eb2 16 character code specification 0c00 16 0c02 16 : 0c0c 16 0c0e 16 0e00 16 0e02 16 0c10 16 0c12 16 : 0c1c 16 0c1e 16 0e08 16 0e0a 16 0c20 16 0c22 16 : 0c2c 16 0c2e 16 0e10 16 0e12 16 0c30 16 0c32 16 : 0c3c 16 0c3e 16 0e18 16 0e1a 16 0c40 16 0c42 16 : 0c4c 16 0c4e 16 0e20 16 0e22 16 0c50 16 0c52 16 : 0c5c 16 0c5e 16 0e28 16 0e2a 16 0c60 16 0c62 16 : 0c6c 16 0c6e 16 0e30 16 0e32 16 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 191 rev. 1.0 table 2.16.6 contents of osd ram (33rd to 42nd character) (continued) display position (from left) 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character block block 8 block 9 block 10 block 11 block 12 block 13 block 14 character code specification 0c70 16 0c72 16 : 0c7c 16 0c7e 16 0e38 16 0e3a 16 0d00 16 0d02 16 : 0d0c 16 0d0e 16 0e40 16 0e42 16 0d10 16 0d12 16 : 0d1c 16 0d1e 16 0e48 16 0e4a 16 0d20 16 0d22 16 : 0d2c 16 0d2e 16 0e50 16 0e52 16 0d30 16 0d32 16 : 0d3c 16 0d3e 16 0e58 16 0e5a 16 0d40 16 0d42 16 : 0d4c 16 0d4e 16 0e60 16 0e62 16 0d50 16 0d52 16 : 0d5c 16 0d5e 16 0e68 16 0e6a 16 color code 1 specification 0c71 16 0c73 16 : 0c7d 16 0c7f 16 0e39 16 0e3b 16 0d01 16 0d03 16 : 0d0d 16 0d0f 16 0e41 16 0e43 16 0d11 16 0d13 16 : 0d1d 16 0d1f 16 0e49 16 0e4b 16 0d21 16 0d23 16 : 0d2d 16 0d2f 16 0e51 16 0e53 16 0d31 16 0d33 16 : 0d3d 16 0d3f 16 0e59 16 0e5b 16 0d41 16 0d43 16 : 0d4d 16 0d4f 16 0e61 16 0e63 16 0d51 16 0d53 16 : 0d5d 16 0d5f 16 0e69 16 0e6b 16 color code 2 specification 0cf0 16 0cf2 16 : 0cfc 16 0cfe 16 0eb8 16 0eba 16 0d80 16 0d82 16 : 0d8c 16 0d8e 16 0ec0 16 0ec2 16 0d90 16 0d92 16 : 0d9c 16 0d9e 16 0ec8 16 0eca 16 0da0 16 0da2 16 : 0dac 16 0dae 16 0ed0 16 0ed2 16 0db0 16 0db2 16 : 0dbc 16 0dbe 16 0ed8 16 0eda 16 0dc0 16 0dc2 16 : 0dcc 16 0dce 16 0ee0 16 0ee2 16 0dd0 16 0dd2 16 : 0ddc 16 0dde 16 0ee8 16 0eea 16 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 192 rev. 1.0 table 2.16.7 contents of osd ram (33rd to 42nd character) (continued) display position (from left) 33rd character 34th character : 39th character 40th character 41st character 42nd character 33rd character 34th character : 39th character 40th character 41st character 42nd character block block 15 block 16 character code specification 0d60 16 0d62 16 : 0d6c 16 0d6e 16 0e70 16 0e72 16 0d70 16 0d72 16 : 0d7c 16 0d7e 16 0e78 16 0e7a 16 color code 1 specification 0d61 16 0d63 16 : 0d6d 16 0d6f 16 0e71 16 0e73 16 0d71 16 0d73 16 : 0d7d 16 0d7f 16 0e79 16 0e7b 16 color code 2 specification 0de0 16 0de2 16 : 0dec 16 0dee 16 0ef0 16 0ef2 16 0df0 16 0df2 16 : 0dfc 16 0dfe 16 0ef8 16 0efa 16 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 193 rev. 1.0 figure 2.16.25 structure of osd ram bit c0 c1 c2 c3 c4 c5 c6 c7 c8 rc11 rc12 rc13 rc14 rc15 rc16 rc17 rc20 rc21 c9 bit name character code (low-order 9 bits) color palette selection bit 0 color palette selection bit 1 color palette selection bit 2 color palette selection bit 3 color palette selection bit 0 color palette selection bit 1 out2 output control color palette selection bit 2 color palette selection bit 3 character code (high-order 1 bit) function specify character code in osd rom specify color palette for character (see note 3) specify color palette for character (see note 3) 0: out2 output off 1: out2 output on specify color palette for background (see note 3) specify character code in osd rom bit name cd code (7 bits) not used color palette selection bit 0 color palette selection bit 1 color palette selection bit 2 color palette selection bit 3 out2 output control not used not used function specify character code in osd rom (color dot) specify a dot which selects color palette 0 by osd rom (see note 4) 0: out2 output off 1: out2 output on character osds/l/p mode cdosd mode notes 1: read value of bits 3 to 7 of the color code 2 is undefined. 2: for not used bits, the write value is read. 3: refer to figure 2.16.26. 4: only in cdosd mode, a dot which selects color palette 0 is colored to the color palette set by rc13 to rc16 of osd ram in character units. when the character size is 1.5t c 5 1h or 1.5t c 5 1/2h, however, set rci3 to rc16 and rc17 of all characters (including the 3nth character) within the same block to the same value. cc mode bit name character code (low-order 9 bits) color palette selection bit 0 color palette selection bit 1 color palette selection bit 2 italic control flash control underline control out2 output control color palette selection bit 0 color palette selection bit 1 character code (high-order 1 bit) character background character background character dot color function specify character code in osd rom specify color palette for character (see note 3) 0: italic off 1: italic on 0: flash off 1: flash on 0: underline off 1: underline on 0: out2 output off 1: out2 output on specify color palette for background (see note 3) specify character code in osd rom blocks 1 to 16 c6 c5 c4 c3 c2 c1 c0 c7 b0 b7 character code rc17 rc16 rc15 rc14 rc13 rc12 rc11 c8 b0 b7 color code 1 color code 2 b0 rc21 rc20 b1 c9 b2 character background M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 194 rev. 1.0 (3) osd ram (osd ram for sprite, addresses 1000 16 to 13e7 16 ) the osd ram for sprite fonts 1 and 2, consisting of 4 planes for each font, is assigned to ad- dresses 1000 16 to 13e7 16 . each plane corresponds to each color palette selection bit and the color palette of each dot is determined from among 16 kinds. table 2.16.8 osd ram address (sprite font 1) dot number dot structure of sprite font plane 2 plane 3 plane 1 plane 0 line number planes plane 3 plane 2 plane 1 plane 0 (color paleltte selection bit 3) (color paleltte selection bit 2) (color paleltte selection bit 1) (color paleltte selection bit 0 ) dots 1 to 8 9 to 16 17 to 24 25 to 32 1 to 8 9 to 16 17 to 24 25 to 32 1 to 8 9 to 16 17 to 24 25 to 32 1 to 8 9 to 16 17 to 24 25 to 32 bits b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 line 1 10c0 16 10c1 16 11c0 16 11c1 16 1080 16 1081 16 1180 16 1181 16 1040 16 1041 16 1140 16 1141 16 1000 16 1001 16 1100 16 1101 16 line 2 10c2 16 10c3 16 11c2 16 11c3 16 1082 16 1083 16 1182 16 1183 16 1042 16 1043 16 1142 16 1143 16 1002 16 1003 16 1102 16 1103 16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? line 19 10e4 16 10e5 16 11e4 16 11e5 16 10a4 16 10a5 16 11a4 16 11a5 16 1064 16 1065 16 1164 16 1165 16 1024 16 1025 16 1124 16 1125 16 line 20 10e6 16 10e7 16 11e6 16 11e7 16 10a6 16 10a7 16 11a6 16 11a7 16 1066 16 1067 16 1166 16 1167 16 1026 16 1027 16 1126 16 1127 16 planes plane 3 plane 2 plane 1 plane 0 (color paleltte selection bit 3) (color paleltte selection bit 2) (color paleltte selection bit 1) (color paleltte selection bit 0 ) dots 1 to 8 9 to 16 17 to 24 25 to 32 1 to 8 9 to 16 17 to 24 25 to 32 1 to 8 9 to 16 17 to 24 25 to 32 1 to 8 9 to 16 17 to 24 25 to 32 bits b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 b7 to b0 line 1 12c0 16 12c1 16 13c0 16 13c1 16 1280 16 1281 16 1380 16 1381 16 1240 16 1241 16 1340 16 1341 16 1200 16 1201 16 1300 16 1301 16 line 2 12c2 16 12c3 16 13c2 16 13c3 16 1282 16 1283 16 1382 16 1383 16 1242 16 1243 16 1342 16 1343 16 1202 16 1203 16 1302 16 1303 16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? line 19 12e4 16 12e5 16 13e4 16 13e5 16 12a4 16 12a5 16 13a4 16 13a5 16 1264 16 1265 16 1364 16 1365 16 1224 16 1225 16 1324 16 1325 16 line 20 12e6 16 12e7 16 13e6 16 13e7 16 12a6 16 12a7 16 13a6 16 13a7 16 1266 16 1267 16 1366 16 1367 16 1226 16 1227 16 1326 16 1327 16 12345678910111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 12345678910111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 12345678910111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 12345678910111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 table 2.16.9 osd ram address (sprite font 2) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 195 rev. 1.0 2.16.7 character color as shown in figure 2.16.26, there are 16 built-in color codes. color palette 0 is fixed at transparent, and color palette 8 is fixed at black. the remaining 14 colors can be set to any of the 512 colors available. the setting procedure for character colors is as follows: ? cc mode ........................................ 8 kinds color palette selection range (color palettes 0 to 7 or 8 to 15) can be selected by bit 0 of the osd control register 3 (address 0207 16 ). color palettes are set by bits rc11 to rc13 of the osd ram from among the selection range. ? osds/l/p mode ........................... 16 kinds color palettes are set by bits rc11 to rc14 of the osd ram. ? cdosd mode ............................... 16 kinds color palettes are set in dot units according to cd font data. only in cdosd mode, a dot which selects color palette 0 or 8 is colored to the color palette set by rc13 to rc16 of osd ram in character units (refer to figure 2.16.28). ? sprite display ............................ 16 kinds color palettes are set in dot units according to the cd font data. notes 1: color palette 8 is always selected for bordering and solid space output (out 1 output) regardless of the set value in the register. 2: color palette 0 (transparent) and the transparent setting of other color palettes will differ. when there are multiple layers overlapping (on top of each other, piled up), and the priority layer is color palette 0 (transparent), the bottom layer is displayed, but if the priority layer is the transparent setting of any other color palette, the background is displayed without displaying the bottom layer (refer to figure 2.16.28). 2.16.8 character background color the display area around the characters can be colored in with a character background color. character background colors are set in character units. ? cc mode ........................................ 4 kinds color palette selection range (color codes 0 to 3, 4 to 7, 8 to 11, or 12 to 15) can be selected by bits 1 and 2 of the osd control register 3 (address 0207 16 ). color palettes are set by bits rc20 and rc21 of the osd ram from among the selection range. ? osds/l/p mode ........................... 16 kinds color palettes are set by bits rc15, rc16, rc20, and rc21 of the osd ram. note: the character background is displayed in the following part: (character display area) C (character font) C (border). accordingly, the character background color and the color signal for these two sections cannot be mixed. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 196 rev. 1.0 figure 2.16.26 color palette selection color palette 1 color palette 2 color palette 3 color palette 4 color palette 5 color palette 6 color palette 7 color palette 8 (black) color palette 9 color palette 10 color palette 11 color palette 12 color palette 13 color palette 14 color palette 15 color palette 0 (transparent) osds/l/p mode (character, background) cdosd mode (character) (see note 2) sprite display cc mode (character) cc mode (background) any palette can be selected. select one palette in screen units. (see note 1) (see note 1) notes 1: color palettes are selected by osd control register 3 (address 0207 16 ). 2: only in cdosd mode, a dot which selects color palette 0 or 8 is colored to of osd ram in character units. select either palette in screen units. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 197 rev. 1.0 figure 2.16.28 difference between color palette 0 (transparent) and transparent setting of other color palettes figure 2.16.27 set of color palette 0 or 8 in cdosd mode dot area specified to color palette 1 dot area specified to color palette 0 when setting black and blue to color palettes 1 and 2, respectively (only in cdosd mode). set values of osd ram (rc16 to rc13) 0000 transparent black blue 0001 0010 color palette 1 (transparent) color palette 0 (transparent) color palette 2 (blue) color palette 8 (black) layer 1 (cc mode) layer 2 (osds/l mode) when layer 1 has priority. blue transparent (video signal) black 26 dots 20 dots 26 dots 20 dots M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 198 rev. 1.0 figure 2.16.29 osd control register 3 cc mode character color selection bit 0: color palettes 0 to 7 1: color palettes 8 to 15 cc mode character background color selection bits (see note) 0 0: color palettes 0 to 3 0 1: color palettes 4 to 7 1 0: color palettes 8 to 11 1 1: color palettes 12 to 15 b2 b1 must always be set to ? osd control register 3 r w b7 b6 b5 b4 b3 b2 b1 b0 symbol oc3 bit symbol bit name function address 0207 16 when reset 00 16 oc30 oc31 reserved bits oc32 0 note: color palette 8 is always selected for solid space (when out1 output is selected), regardless of value of this register. osds/l/p mode window control bit 0: window off 1: window on oc35 cc mode window control bit 0: window off 1: window on oc36 cdosd mode window control bit 0: window off 1: window on oc37 flash cycle selection bit 0: 1 cycle = v sync cycle 5 32 1: 1 cycle = v sync cycle 5 64 oc34 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 199 rev. 1.0 figure 2.16.30 color palette register i (i = 1 to 7, 9 to 15) color palette register i b7 b6 b5 b4 b3 b2 b1 b0 (b15) b7 (b8) b0 b6 b5 b4 b3 b2 b1 symbol addresses when reset cri (i = 1 to 7) even addresses within addresses 0240 16 to 024d 16 , indeterminate odd addresses within addresses 0240 16 to 024d 16 cri (i = 8 to 15) even addresses within addresses 024e 16 to 025b 16 , indeterminate odd addresses within addresses 024e 16 to 025b 16 bit symbol cri_2 to cri_0 r signal output control bits bit name function r w b2 b1 b0 0 0 0 : v ss 0 0 1 : 1/7v cc 0 1 0 : 2/7v cc 0 1 1 : 3/7v cc 1 0 0 : 4/7v cc 1 0 1 : 5/7v cc 1 1 0 : 6/7v cc 1 1 1 : v cc cri_6 to cri_4 g signal output control bits b2 b1 b0 0 0 0 : v ss 0 0 1 : 1/7v cc 0 1 0 : 2/7v cc 0 1 1 : 3/7v cc 1 0 0 : 4/7v cc 1 0 1 : 5/7v cc 1 1 0 : 6/7v cc 1 1 1 : v cc cri_10 to cri_8 b signal output control bits b2 b1 b0 0 0 0 : v ss 0 0 1 : 1/7v cc 0 1 0 : 2/7v cc 0 1 1 : 3/7v cc 1 0 0 : 4/7v cc 1 0 1 : 5/7v cc 1 1 0 : 6/7v cc 1 1 1 : v cc cri_12 out1 signal output control bit 0: no output 1: output nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 200 rev. 1.0 2.16.9 out1, out2 signals the out1, out2 signals are used to control the luminance of the video signal. the output waveform of the out1, out2 signals is controlled by bit 6 of the color palette register i (refer to figure 2.16.30), bits 0 to 2 of the block control register i (refer to figure 2.16.4) and rc17 of osd ram. the setting values for controlling out1, out2 and the corresponding output waveform is shown in figure 2.16.31. figure 2.16.31 setting value for controlling out1, out2 and corresponding output waveform h notes 1: this control is only valid in the osds/p mode. it is invalid in cc/cdosd/osdl mode . 2: in the cdosd mode, coloring is performed for each dot. accordingly, out1 outputs to dots which bit 12 (cri12) of the color pallet register i is set to ?. 3: out2 cannot be output in sprite osd. 4: 5 is an arbitrary value. l l h l h l h l h l h l h l h l h l h out1 signal output control bit (see note 2) bit12(cri12) of color pallet register i border output out2 output control (rc 17 of os d ram ) back g round character 0 1 no output output (see n o t e 1 ) 0 1 0 1 0 1 5 5 0 1 0 1 0 1 5 5 5 5 5 out2 si g nal out1 si g nal conditions output waveform M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 201 rev. 1.0 2.16.10 attribute the attributes (flash, underline, italic fonts) are controlled to the character font. the attributes for each character are specified by rc14 to rc16 of osd ram (refer to figure 2.16.26). the attributes to be controlled are different depending on each mode. cc mode ................... flash, underline, italic for each character osds/p mode .......... border (all bordered, shadow bordered can be selected) for each block (1) under line the underline is output at the 23rd and 24th lines in vertical direction only in the cc mode. the underline is controlled by rc16 of osd ram. the color of underline is the same color as that of the character font. (2) flash the parts of the character font, the underline, and the character background are flashed only in the cc mode. the flash for each character is controlled by rc15 of osd ram. the on/off for flash is controlled by bit 3 of the osd control register 1 (refer to figure 2.16.3). when this bit is 0, only character font and underline flash. when 1, for a character without solid space output, r, g, b and out1 (all display area) flash, for a character with solid space output, only r, g, and b (all display area) flash. the flash cycle bases on the v sync count. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 202 rev. 1.0 figure 2.16.32 example of attribute display (in cc mode) 0 1 b i t 6 b i t 4 ( d ) u n d e r l i n e a n d i t a l i c ( p r e - d i v i d e r a t i o = 2 ) c o l o r c o d e 1 0 1 b i t 6 b i t 4 ( c ) i t a l i c ( p r e - d i v i d e r a t i o = 1 ) c o l o r c o d e 1 0 0 c o l o r c o d e 1 b i t 6b i t 4 ( a ) o r d i n a r y 10 c o l o r c o d e 1 b i t 6b i t 4 ( b ) u n d e r l i n e ( e ) u n d e r l i n e a n d i t a l i c a n d f l a s h 1 b i t 4 ( r c 1 6 ) b i t 5 ( r c 1 5 ) c o l o r c o d e 1 1 b i t 6 ( r c 1 6 ) f l a s h f l a s h f l a s h o f f o n o f f o n M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 203 rev. 1.0 figure 2.16.33 example of italic display 10 0 1 1 0 1 (refer to 12.16.10 notes 5, 6) (refer to 12.16.10 notes 6, 7) bit 4 of color code 1 notes 1 : the dotted line is the boundary of character color. 2: when bit 4 of osd control register 1 is 0. 32nd chracter 26th chracter M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 204 rev. 1.0 (4) border the border is output in the osds/p mode. the all bordered (bordering around of character font) and the shadow bordered (bordering right and bottom sides of character font) are selected (refer to figure 2.16.34) by bit 2 of the osd control register 1 (refer to figure 2.16.3). the on/off switch for borders can be controlled in block units by bits 0 to 2 of the block control register i (refer to figure 2.16.4). the out1 signal is used for border output. the border color is fixed at color palette 8 (block). the border color for each screen is specified by the border color register i. the horizontal size (x) of border is 1t c (osd clock cycle divided in the pre-divide circuit) regardless of the character font dot size. however, only when the pre-divide ratio = 2 and character size = 1.5t c , the horizontal size is 1.5t c . the vertical size (y) different depending on the screen scan mode and the vertical dot size of character font. notes 1 : the border dot area is the shaded area as shown in figure 2.16.36. 2 : when the border dot overlaps on the next character font, the character font has priority (refer to figure 2.16.37 a). when the border dot overlaps on the next character back ground, the border has priority (refer to figure 2.16.37 b). 3 : the border in vertical out of character area is not displayed (refer to figure 2.16.38). figure 2.16.34 example of border display figure 2.16.35 horizontal and vertical size of border all bordered shadow bordered y x 1/2h 1h, 2h, 3h 1/2h, 1h, 2h, 3h 1/2h 1h 1h vertical dot size of character font border dot size scan mode horizontal size (x) vertical size (y) normal scan mode bi-scan mode 1t c (osd clock cycle divided in pre-divide circuit) 1.5t c when selecting 1.5t c for character size. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 205 rev. 1.0 figure 2.16.36 border area figure 2.16.37 border priority osds/l/p mode 1 dot width of border 1 dot width of border 16 dot s character font area 20 dots 12 dots 20 dots 1 dot width of border 1 dot width of border character boundary b character boundary a character boundary b M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 206 rev. 1.0 0 01 table 2.16.10 setting for automatic solid space 01 bit 4 of osd control register 1 bit 3 of osd control register 2 rc17 of osd ram out1 output signal out2 output signal 2.16.11 automatic solid space function this function generates automatically the solid space (out1 or out2 blank output) of the character area in the cc mode. the solid space is output in the following area : ? the character area except character code 009 16 ?the character area on the left and right sides this function is turned on and off by bit 4 of the osd control register 1 (refer to figure 2.16.3). out1 or out2 output is selected by bit 3 of the osd control register 2. notes 1: when selecting out1 as solid space output, character background color with solid space output is fixed to color palette 8 (black) regardless of setting. 2: when selecting any font except blank font as the character code 009 16 , the set font is output. 0 1 figure 2.16.38 display screen example of automatic solid space off ?character font area ?character background area 0 ?character display area 01 off ?character font area ?character background area 1 off ?solid space area ?character display area ?character display area 1 01 ?solid space ? solid space ?character display area ?character font area ?character background area 005 009 009 009 006 006 16 16 16 16 16 16 006 16 ? ? ? ? ? ? when setting the character code 005 16 as the character a, 006 16 as the character b. (osd ram) (display screen) 2nd character no solid space output 32nd character (in 32-character mode) 42nd character (in 42-character mode) 1st character M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 207 rev. 1.0 2.16.12 particular osd mode block this function can display with mixing the fonts below within the osdp mode block. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 208 rev. 1.0 table 2.16.11 corresponding between character codes and display fonts character code notes display fonts 000 16 to 0ef 16 , 100 16 to 2ff 16 (except 100 16 , 180 16 , 200 16 , 280 16 ) 0f0 16 to 0fd 16 ? the left 12-dot part (16 5 12 dots) of set font is displayed. in cc and osds modes, entire part (16 5 20 dots) of set font is displayed. the blank font (only character background) is displayed. any character is not displayed on the right side area nor any following areas of this font. do not set this font for the 1st character (left edge) of a block. the blank font (only character background) is displayed. any character is not displayed on the right side area nor any following areas of this font. do not set this font for the 1st character (left edge) of a block. 3fe 16 3ff 16 8 dots 20 dots 4 dots 20 dots 20 dots 12 dots not displayed 20 dots 16 dots M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 209 rev. 1.0 2.16.13 multiline display this microcomputer can ordinarily display 16 lines on the crt screen by displaying 16 blocks at different vertical positions. in addition, it can display up to 16 lines by using osd1 interrupts. an osd1 interrupt request occurs at the point at which display of each block has been completed. in other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block. the mode in which an osd1 interrupt occurs is different depending on the setting of the osd control register 2 (refer to figure 2.16.7). ? when bit 7 of the osd control register 2 is 0 an osd1 interrupt request occurs at the completion of layer 1 block display. ? when bit 7 of the osd control register 2 is 1 an osd1 interrupt request occurs at the completion of layer 2 block display. notes 1: an osd1 interrupt does not occur at the end of display when the block is not displayed. in other words, if a block is set to off display by the display control bit of the block control register i (addresses 0210 16 to 021f 16 ), an osd1 interrupt request does not occur (refer to figure 2.16.41 (a)). 2: when another block display appears while one block is displayed, an osd1 interrupt request occurs only once at the end of the another block display (refer to figure 2.16.40 (b)). 3: on the screen setting window, an osd1 interrupt occurs even at the end of the cc mode block (off display) out of window (refer to figure 2.16.40 (c)). figure 2.16.40 note on occurrence of osd1 interrupt (b) (c) block 1 (on display) block 2 (on display) block 3 (on display) block 4 (on display) block 1 (on display) block 2 (on display) block 3 (off display) block 4 (off display) osd1 interrupt request osd1 interrupt request osd1 interrupt request osd1 interrupt request osd1 interrupt request osd1 interrupt request no osd1 interrupt request block 1 block 2 osd1 interrupt request osd1 interrupt request osd1 interrupt request osd1 interrupt request block 1 block 2 block 3 on display (osd1 interrupt request occurs at the end of block display) off display (osd1 interrupt request does not occur at the end of block display) window no osd1 interrupt request no osd1 interrupt request (a) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 210 rev. 1.0 2.16.14 sprite osd function this is especially suitable for cursor and other displays as its function allows for display in any position, regardless of the validity of block osd displays or display positions. sprite font consists of 2 charac- ters: sprite fonts 1 and 2. each sprite font is a ram font consisting of 32 horizontal dots 5 20 vertical dots, 4 planes, and 4 bits of data per dot. each plane has corresponding color palette selection bit, and 16 kinds of color palettes can be selected by the plane bit combination (three bits) for each dot. the color palette is set in dot units according to the osd ram (sprite) contents from among the selection range. it is possible to add arbitrary font data by software as the sprite fonts consist of ram font. the sprite osd control register can control sprite display and dot size. the display position can also be set independently of the block display by the sprite horizontal position registers and the sprite horizontal vertical position registers. the vertical fonts 1 and 2 can be set independently. an osd inter- rupt request occurs at each completion of font display. the horizontal position is set in 2048 steps in 2t osc units, and the vertical position is set in 1024 steps in 1t h units. when sprite display overlaps with other osd displays, sprite display is always given priority. how- ever, the sprite display overlaps with the display which includes out2 output, out2 in the osd is output without masking. notes 1: the sprite osd function cannot output out2. 2: when using sprite osd, do not set hs 003 16 , hs 3 800 16 . 3: when using sprite osd, do not set vsi = 000 16 , vsi 3 400 16 . 4: when displaying with sprite fonts 1 and 2 overlapped, the sprite font with a larger set value as the vertical display start position is displayed. when the set values of the vertical display start position are the same, the sprite font 1 is displayed. figure 2.16.41 sprite osd display example video adjustment tint C ? ? | ? ? + contrast C ? ? | ? ? + color tone C ? ? | ? ? + picture C ? ? | ? ? + brightness C ? ? | ? ? + example of sprite display ...... dot 1 ...... example of sprite font line 1 line 20 ...... sprite font 1 sprite font 2 ...... dot 32 dot 17 dot 16 line 1 line 20 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 211 rev. 1.0 figure 2.16.42 sprite osd control register sprite font 1 control bit b3 b2 0 0: 1tc 5 1/2h 0 1: 1tc 5 1h 1 0: 2tc 5 1h 1 1: 2tc 5 2h dot size selection bits sprite font 2 control bit pre-divide ratio selection bit 0: pre-divide ratio 1 1: pre-divide ratio 2 0: do not display 1: display 0: do not display 1: display notes 1: tc is osd clock cycle divided in pre-divide circuit. 2: h is h sync b7 b6 b5 b4 b3 b2 b1 b0 sprite osd control register bit symbol bit name function symbol sc address 0201 16 when reset xxx00000 2 r w sc0 sc1 sc2 sc4 sc3 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 212 rev. 1.0 figure 2.16.43 sprite horizontal position register figure 2.16.44 sprite vertical position register i (i = 1, 2) sprite horizontal position register b7 b6 b5 b4 b3 b2 b1 b0 (b15) b7 (b8) b0 b6 b5 b4 b3 b2 b1 symbol address when reset hs 0279 16 , 0278 16 indeterminate bit symbol hs10 to hs0 horizontal display start position control bits of sprite font bit name function r w horizontal display start position = 2t osc 5 n (n: setting value, t osc : osd oscillation cycle) nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. note : do not set hs 003 16 , hs 3 800 16 . sprite vertical position register i b7 b6 b5 b4 b3 b2 b1 b0 (b15) b7 (b8) b0 b6 b5 b4 b3 b2 b1 symbol address when reset vs1 0275 16 , 0274 16 indeterminate vs2 0277 16 , 0276 16 indeterminate bit symbol vsi9 to vsi0 vertical display start position control bits of sprite font i (i = 1, 2) bit name function r w vertical display start position = t h 5 n (n: setting value, t h : h sync cycle) nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. note : do not set vsi = 000 16 , vsi 3 400 16 (i = 1, 2). M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 213 rev. 1.0 2.16.15 window function the window function can be set windows on-screen and output osd within only the area where the window is set. the on/off for vertical window function is performed by bit 5 of the osd control register 1 and is used to select vertical window function or vertical blank function by bit 6 of the osd control register 2. accord- ingly, the vertical window function cannot be used simultaneously with the vertical blank function. the display mode to validate the window function is selected by bits 5 to 7 of the osd control register 3. the top border is set by the top border control register (tbr) and the bottom border is set by the bottom border control register (bbr). the on/off for horizontal window function is performed by bit 4 of the osd control register 2 and is used interchangeably for the horizontal blank function with bit 5 of the osd control register 2. accord- ingly, the horizontal blank function cannot be used simultaneously with the horizontal window function. the display mode to validate the window function is selected by bits 5 to 7 of the osd control register 3. the left border is set by the left border control register (lbr), and the right border is set by the right border control register (rbr). notes 1: horizontal blank and horizontal window, as well as vertical blank and vertical window can not be used simultaneously. 2: when the window function is on by osd control registers 1 and 2, the window function of out2 is valid in all display mode regardless of setting value of the osd control register 3 (bits 5 to 7). for example, even when make the window function valid in only cc mode, the function of out2 is valid in osds/l/p and cdosd modes. 3: as for sprite display, the window function does not operate. figure 2.16.45 example of window function (when cc mode is valid) cdosd mode fgh ij klmno pqrst osds/l/p mode abcde uvwxy screen cc mode window bottom border of window top border of window right border of window left border of window window M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 214 rev. 1.0 2.16.16 blank function the blank function can output blank (out1) area on all sides (vertical and horizontal) of the screen. this provides the blank signal, wipe function, etc., when outputting a 3 : 4 image on a wide screen. the on/off for vertical blank function is performed by bit 5 of the osd control register 1 and is used to select vertical window function or vertical blank function by bit 6 of the osd control register 2. accord- ingly, the vertical blank function cannot be used simultaneously with the vertical window function. the top border is set by the top border control register (tbr), and the bottom border is set by the bottom border control register (bbr), in 1h units. the on/off for horizontal blank function is performed by bit 4 of the osd control register 2 and is used interchangeably for the horizontal window function with bit 5 of the osd control register 2 . accordingly, the horizontal blank function cannot be used simultaneously with the horizontal window function. the left border is set by the left border control register (lbr) and the right border is set by the right border control register (rbr), in 4t osc units. the osd output (except raster) in area with blank output is not deleted. these blank signals are not output in the horizontal/vertical blanking interval. notes 1. horizontal blank and horizontal window, as well as vertical blank and vertical window can not be used simultaneously. 2. when using the window function, be sure to set 1 to bit 0 of osd control register 1. figure 2.16.46 blank output example (when osd output is b + out1) output example of horizontal blank output example of top and vertical blank out1 out1 4 a' a b 4 a a' b blank output signal in microcomputer blank output signal in microcomputer h l h l h l h l h l h l M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 215 rev. 1.0 figure 2.16.47 top border control register top border control register b7 b6 b5 b4 b3 b2 b1 b0 (b15) b7 (b8) b0 b6 b5 b4 b3 b2 b1 symbol address when reset tbr 020d 16 , 020c 16 indeterminate bit symbol tbr_9 to tbr_0 top border control bits bit name function r w top border position = t h 5 n (n: setting value, t h : h sync cycle) nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. notes 1 : do not set tbr 001 16 , tbr 3 400 16 . 2 : set as tbr < bbr. figure 2.16.48 bottom border control register bottom border control register b7 b6 b5 b4 b3 b2 b1 b0 (b15) b7 (b8) b0 b6 b5 b4 b3 b2 b1 symbol address when reset bbr 020f 16 , 020e 16 indeterminate bit symbol bbr_9 to bbr_0 bottom border control bits bit name function r w bottom border position = t h 5 n (n: setting value, t h : h sync cycle) nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. notes 1 : do not set bbr 3 400 16 . 2 : set as tbr < bbr. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 216 rev. 1.0 figure 2.16.49 left border control register figure 2.16.50 bottom border control register left border control register b7 b6 b5 b4 b3 b2 b1 b0 (b15) b7 (b8) b0 b6 b5 b4 b3 b2 b1 symbol address when reset lbr 0271 16 , 0270 16 xxxxx00000000001 2 bit symbol lbr_10 to lbr_0 left border control bits bit name function r w left border position = 4t osc 5 n (n: setting value, t osc : osd oscillation cycle) nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. notes 1 : do not set lbr 003 16 , lbr 3 800 16 . 2 : set as lbr < rbr. right border control register b7 b6 b5 b4 b3 b2 b1 b0 (b15) b7 (b8) b0 b6 b5 b4 b3 b2 b1 symbol address when reset rbr 0273 16 , 0272 16 xxxxx00000000000 2 bit symbol rbr_10 to rbr_0 right border control bits bit name function r w left border position = 4t osc 5 n (n: setting value, t osc : osd oscillation cycle) nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. notes 1 : do not set rbr 3 800 16 . 2 : set as lbr < rbr. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 217 rev. 1.0 2.16.17 raster coloring function an entire screen (raster) can be colored by setting the bits 6 to 0 of the raster color register. since each of the r, g, b, out1, and out2 pins can be switched to raster coloring output, 512 raster colors can be obtained. when the character color/the character background color overlaps with the raster color, the color (r, g, b, out1, out2), specified for the character color/the character background color, takes priority of the raster color. this ensures that the character color/the character background color is not mixed with the raster color. the raster color register is shown in figure 2.16.51, the example of raster coloring is shown in figure 2.16.52. note: raster is not output to the area which includes blank area. figure 2.16.51 raster color register raster color register b7 b6 b5 b4 b3 b2 b1 b0 (b15) b7 (b8) b0 b6 b5 b4 b3 b2 b1 symbol address when reset rsc 0209 16 , 0208 16 0000 16 bit symbol rsc2 to rsc0 r singnal output control bits bit name function r w b2 b1 b0 0 0 0 : v ss 0 0 1 : 1/7v cc 0 1 0 : 2/7v cc 0 1 1 : 3/7v cc 1 0 0 : 4/7v cc 1 0 1 : 5/7v cc 1 1 0 : 6/7v cc 1 1 1 : v cc rsc6 to rsc4 g singnal output control bits b6 b5 b4 0 0 0 : v ss 0 0 1 : 1/7v cc 0 1 0 : 2/7v cc 0 1 1 : 3/7v cc 1 0 0 : 4/7v cc 1 0 1 : 5/7v cc 1 1 0 : 6/7v cc 1 1 1 : v cc rsc10 to rsc8 b singnal output control bits b10 b9 b8 0 0 0 : v ss 0 0 1 : 1/7v cc 0 1 0 : 2/7v cc 0 1 1 : 3/7v cc 1 0 0 : 4/7v cc 1 0 1 : 5/7v cc 1 1 0 : 6/7v cc 1 1 1 : v cc rsc12 out1 singnal output control bit 0: no output 1: output nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. rsc13 out2 singnal output control bit 0: no output 1: output nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. nothing is assined. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 218 rev. 1.0 figure 2.16.52 example of raster coloring h sync a' a out1 r g b h sync a' a out1 r g b : character color red (r and out1) : border color black (out1) : background color magenta (r, b and out1) : raster color blue (b and out1) signals across a-a' blank control signal in microcomputer : horizontal blank (out1) : character color red (r and out1) : border color black (out1) : background color magenta (r, b and out1) : raster color blue (b and out1) signals across a-a' M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 219 rev. 1.0 2.16.18 scan mode this microcomputer has the bi-scan mode for corresponding to h sync of double speed frequency. in the bi-scan mode, the vertical start display position and the vertical size is two times as compared with the normal scan mode. the scan mode is selected by bit 1 of the osd control register 1 (refer to figure 2.16.3). bit 1 of osd control register 1 vertical display start position vertical dot size table 2.16.12 setting for scan mode normal scan 0 value of vertical position register 5 1h 1t c 5 1/2h 1t c 5 1h 2t c 5 2h 3t c 5 3h bi-scan 1 value of vertical position register 5 2h 1t c 5 1h 1t c 5 2h 2t c 5 4h 3t c 5 6h scan mode parameter 2.16.19 r, g, b signal output control the form of r, g, b signal output is controlled by bit 2 of the osd control register 2 as the table below. 0 1 table 2.16.13 r, g, b signal output control bit 2 of osd control register 2 each r, g, b pin outputs 2 values (digital output). each r, g, b pin outputs 8 values (analog output). form of r, g, b signal output M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 220 rev. 1.0 figure 2.16.53 osd reserved register i (i=1, 2) 2.16.20 osd reserved register osd reserved register i (i=1, 2) symbol address when reset or1 025d 16 00 16 or2 027c 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 reserved bit s bit symbol bit name description rw mest always be sed to 0 000 0 0 00 0 figure 2.16.54 osd reserved register 3 osd reserved register 3 symbol address when reset or3 027b 16 xx000000 2 b7 b6 b5 b4 b3 b2 b1 b0 reserved bit s bit symbol bit name description rw mest always be set to 0 000 0 0 00 0 reserved bit s mest always be set to 0 figure 2.16.55 osd reserved register 4 osd reserved register 4 symbol address when reset or4 027a 16 xx000000 2 b7 b6 b5 b4 b3 b2 b1 b0 reserved bit bit symbol bit name description rw mest always be set to 1 00 0 1 00 0 0 reserved bits mest always be set to 0 reserved bit mest always be set to 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 221 rev. 1.0 2.17 programmable i/o ports there are 46 programmable i/o ports: p0 0 Cp0 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 3 , p5 0 , p5 2 , p5 3 , p6 2 , p6 3 , p6 7 , p7 0 Cp7 2 , p7 4 , p7 6 , p8 2 , p9 0 , p9 3 , p9 4 , p10 0 and p10 1 . each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. figures 2.17.1 to 2.17.3 show the programmable i/o ports. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices (other than the d-a con- verter), they function as outputs regardless of the contents of the direction registers. when pins are to be used as the outputs for the d-a converter, do not set the direction registers to output mode. see the descriptions of the respective functions for how to set up the built-in peripheral devices. 2.17.1 direction registers figures 2.17.5 to 2.17.12 show the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these regis- ters corresponds one for one to each i/o pin. (1) effect of the protection register data written to the direction register of p9 is affected by the protection register. the direction register of p9 cannot be easily written. 2.17.2 port registers figures 2.17.13 to 2.17.20 show the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. (1) reading a port register with the direction register set to output, reading a port register takes out the content of the port regis- ter, not the content of the pin. with the direction register set to input, reading the port register takes out the content of the pin. (2) writing to a port register with the direction register set to output, the level of the written values from each relevant pin is output by writing to a port register. writing to the port register, with the direction register set to input, inputs a value to the port register, but nothing is output to the relevant pins. the output level remains floating. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 222 rev. 1.0 2.17.3 pull-up control registers figures 2.17.24 to 2.17.26 show the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 223 rev. 1.0 figure 2.17.1 programmable i/o ports (1) d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h p 0 0 p 0 7 , p 2 0 p 2 7 , p 3 0 ? 3 2 , p 5 0 ? 5 3 p u l l - u p s e l e c t i o n p 3 4 , p 3 5 , p 6 2 , p 9 0 , p 1 0 0 , p 1 0 1 p u l l - u p s e l e c t i o n d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s ( n o t e ) ( n o t e ) s y m b o l i z e s a p a r a s i t i c s d i o d e . d o n o t a p p l y a v o l t a g e h i g h e r t h a n v c c e a c h p o r t . n o t e : p 3 3 , p 8 2 d a t a b u s p u l l - u p s e l e c t i o n i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s d i r e c t i o n r e g i s t e r p o r t l a t c h ( n o t e ) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 224 rev. 1.0 figure 2.17.2 programmable i/o ports (2) p 7 0 , p 7 1 i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s d a t a b u s p 5 5 d a t a b u s p u l l - u p s e l e c t i o n i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s d a t a b u s p 6 3 , p 7 4 , p 7 6 p u l l - u p s e l e c t i o n o u t p u t 1 d i r e c t i o n r e g i s t e r p o r t l a t c h d i r e c t i o n r e g i s t e r p o r t l a t c h o u t p u t 1 d i r e c t i o n r e g i s t e r p o r t l a t c h o u t p u t 1 ( n o t e ) ( n o t e ) ( n o t e ) s y m b o l i z e s a p a r a s i t i c s d i o d e . d o n o t a p p l y a v o l t a g e h i g h e r t h a n v c c e a c h p o r t . n o t e : M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 225 rev. 1.0 figure 2.17.3 programmable i/o ports (3) p 9 3 , p 9 4 a n a l o g o u t p u t d - a o u t p u t e n a b l e d i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s p 3 6 , p 3 7 , p 4 0 p 4 3 p 6 7 , p 7 2 d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s s y m b o l i z e s a p a r a s i t i c s d i o d e . d o n o t a p p l y a v o l t a g e h i g h e r t h a n v c c e a c h p o r t . n o t e : ( n o t e ) p u l l - u p s e l e c t i o n a n a l o g i n p u t d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h d a t a b u s p u l l - u p s e l e c t i o n i n p u t t o r e s p e c t i v e p e r i p h e r a l f u n c t i o n s s d a 2 , s c l 2 s e l e c t 1 o u t p u t d i r e c t i o n r e g i s t e r p o r t l a t c h ( n o t e ) d - a o u t p u t e n a b l e d p u l l - u p s e l e c t i o n ( n o t e ) s d a 3 , s c l 3 s e l e c t 1 o u t p u t M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 226 rev. 1.0 figure 2.17.4 i/o pins cnv ss cnv ss signal input reset reset signal input notes1: symbolizes a parasitic diode. don't apply a voltage higher than vcc to each pin. 2: a parasitic diode on the v cc side is added to the mask rom version. don't apply a voltage higher than vcc to each pin. (note 2) (note 1) (note 1) r, g, b internal circuit out1, out2 (note) internal circuit ..... ..... ..... ..... (note) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 227 rev. 1.0 figure 2.17.5 port pi direction register (i = 0, 2, 3) figure 2.17.6 port p4 direction register p o r t p i d i r e c t i o n r e g i s t e r s y m b o la d d r e s sw h e n r e s e t p d i ( i = 0 , 2 , 3 ) 0 3 e 2 1 6 , 0 3 e 6 1 6 , 0 3 e 7 1 6 , 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o lw r b 7b 6b 5b 4b 3b 2b 1b 0 p d i _ 0p o r t p i 0 d i r e c t i o n r e g i s t e r p d i _ 1p o r t p i 1 d i r e c t i o n r e g i s t e r p d i _ 2p o r t p i 2 d i r e c t i o n r e g i s t e r p d i _ 3p o r t p i 3 d i r e c t i o n r e g i s t e r p d i _ 4p o r t p i 4 d i r e c t i o n r e g i s t e r p d i _ 5p o r t p i 5 d i r e c t i o n r e g i s t e r p d i _ 6p o r t p i 6 d i r e c t i o n r e g i s t e r p d i _ 7p o r t p i 7 d i r e c t i o n r e g i s t e r 0 : i n p u t m o d e ( f u n c t i o n s a s a n i n p u t p o r t ) 1 : o u t p u t m o d e ( f u n c t i o n s a s a n o u t p u t p o r t ) ( i = 0 , 2 , 3 ) port p4 direction register symbol address when reset pd4 03ea 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd4_0 port p4 0 direction register pd4_1 port p4 1 direction register pd4_2 port p4 2 direction register pd4_3 port p4 3 direction register reserved bits 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 111 must always be set to ? 1 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 228 rev. 1.0 figure 2.17.8 port p6 direction register figure 2.17.7 port p5 direction register port p5 direction register symbol address when reset pd5 03eb 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd5_0 port p5 0 direction register reserved bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 11 1 must always be set to ? 1 pd5_2 port p5 2 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) pd5_3 port p5 3 direction register reserved bit must always be set to ? pd5_5 port p5 5 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) reserved bits must always be set to ? port p6 direction register symbol address when reset pd6 03ee 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 reserved bit 11 1 must always be set to ? 1 pd6_2 port p6 2 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) pd6_3 port p6 3 direction register reserved bit must always be set to ? pd6_7 port p6 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 reserved bit must always be set to ? M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 229 rev. 1.0 figure 2.17.9 port p7 direction register figure 2.17.10 port p8 direction register port p7 direction register symbol address when reset pd7 03ef 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd7_0 port p7 0 direction register reserved bit 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 01 must always be set to ? 0 pd7_1 port p7 1 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) pd7_2 port p7 2 direction register reserved bit must always be set to ? pd7_6 port p7 6 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) reserved bit must always be set to ? pd7_4 port p7 4 direction register port p8 direction register symbol address when reset pd8 03f2 16 00x00000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 11 1 pd8_2 port p8 2 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) reserved bit must always be set to ? 0 reserved bits must always be set to ? 0 0 reserved bit must always be set to ? nothing is assigned. in an attempt to write to these bits, write ?.? the value, if read, turns out to be indeterminate. reserved bits must always be set to ? M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 230 rev. 1.0 figure 2.17.11 port p9 direction register figure 2.17.12 port p10 direction register port p9 direction register symbol address when reset pd9 03f3 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd9_0 port p9 0 direction register reserved bits 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 11 must always be set to ? 1 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) reserved bits must always be set to ? pd9_3 port p9 3 direction register 11 pd9_4 port p9 4 direction register port p10 direction register symbol address when reset pd10 03f6 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd10_0 port p10 0 direction register reserved bits 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 00 must always be set to ? 0 00 pd10_1 port p10 1 direction register 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 231 rev. 1.0 figure 2.17.14 port p4 register figure 2.17.13 port pi register (i = 0, 2, 3) p o r t p i r e g i s t e r s y m b o la d d r e s sw h e n r e s e t p i ( i = 0 , 2 , 3 ) 0 3 e 0 1 6 , 0 3 e 4 1 6 , 0 3 e 5 1 6 i n d e t e r m i n a t e b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 p i _ 0p o r t p i 0 r e g i s t e r p i _ 2p o r t p i 2 r e g i s t e r p i _ 3p o r t p i 3 r e g i s t e r p i _ 5p o r t p i 5 r e g i s t e r p i _ 6p o r t p i 6 r e g i s t e r p i _ 7p o r t p i 7 r e g i s t e r d a t a i s i n p u t a n d o u t p u t t o a n d f r o m e a c h p i n b y r e a d i n g a n d w r i t i n g t o a n d f r o m e a c h c o r r e s p o n d i n g b i t 0 : l l e v e l d a t a 1 : h l e v e l d a t a ( i = 0 , 2 , 3 ) p i _ 4p o r t p i 4 r e g i s t e r p i _ 1p o r t p i 1 r e g i s t e r port p4 register symbol address when reset p4 03e8 16 indeterminate b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 bit name function bit symbol w r p4_0 port p4 0 register p4_2 port p4 2 register p4_3 port p4 3 register reserved bits data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data p4_1 port p4 1 register must always be set to ? 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 232 rev. 1.0 figure 2.17.15 port p5 register figure 2.17.16 port p6 register port p5 register symbol address when reset p5 03e9 16 indeterminate b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 bit name function bit symbol w r p5_0 port p5 0 register reserved bit data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data must always be set to ? 0 p5_2 port p5 2 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data p5_3 port p5 3 register reserved bit must always be set to ? p5_5 port p5 5 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data reserved bits must always be set to ? port p6 register symbol address when reset p6 03ec 16 indeterminate b7 b6 b5 b4 b3 b2 b1 b0 0 00 bit name function bit symbol w r reserved bits must always be set to ? 0 p6_2 port p6 2 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data p6_3 port p6 3 register reserved bit must always be set to ? p6_7 port p6 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 233 rev. 1.0 figure 2.17.17 port p7 register figure 2.17.18 port p8 register port p7 register symbol address when reset p7 03ed 16 indeterminate b7 b6 b5 b4 b3 b2 b1 b0 0 0 bit name function bit symbol w r p7_0 port p7 0 register reserved bit data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data must always be set to ? 0 p7_4 port p7 4 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data reserved bit must always be set to ? p7_6 port p7 6 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data reserved bit must always be set to ? p7_1 port p7 1 register p7_2 port p7 2 register note: since p7 0 and p7 1 are n-channel open-drain ports, the data is high-impedance. port p8 register symbol address when reset p8 03f0 16 indeterminate b7 b6 b5 b4 b3 b2 b1 b0 0 00 bit name function bit symbol w r reserved bits must always be set to ? 0 p8_2 port p8 2 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data reserved bits must always be set to ? 0 00 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 234 rev. 1.0 figure 2.17.19 port p9 register figure 2.17.20 port p10 register port p9 register symbol address when reset p9 03f1 16 indeterminate b7 b6 b5 b4 b3 b2 b1 b0 0 00 bit name function bit symbol w r 0 p9_0 port p9 0 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data reserved bits must always be set to ? p9_3 port p9 3 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data 0 p9_4 port p9 4 register reserved bits must always be set to ? port p10 register symbol address when reset p10 03f4 16 indeterminate b7 b6 b5 b4 b3 b2 b1 b0 0 00 bit name function bit symbol w r 0 p10_0 port p10 0 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data reserved bits must always be set to ? 0 p10_1 port p10 1 register 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 235 rev. 1.0 figure 2.17.21 port reserved register 1 port reserved register 1 symbpl address when reset pr1 03e1 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 reserved bits must always be set to ? 0 0 0 0 0 0 0 0 port reserved register 2 symbpl address when reset pr2 03e3 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 reserved bits must always be set to ? 1 1 1 1 1 1 1 1 port reserved register 3 symbpl address when reset pr3 03ff 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 reserved bit nothing is assigned. in an attempt to write to this bit, write ?.? the value, if read, turns out to be ?. must always be set to ? 0 figure 2.17.22 port reserved register 2 figure 2.17.23 port reserved register 3 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 236 rev. 1.0 figure 2.17.24 pull-up control register 0 figure 2.17.25 pull-up control register 1 pull-up control register 0 symbol address when reset pur0 03fc 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu04 p2 0 to p2 3 pull-up pu05 p2 4 to p2 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high reserved bits must always be set to ? 0 0 pull-up control register 1 symbol address when reset pur1 03fd 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu10 p4 0 to p4 3 pull-up pu12 p5 0 , p5 2 , p5 3 pull-up pu13 p5 5 pull-up pu14 p6 2 , p6 3 pull-up pu15 p6 7 pull-up(note 2) pu16 p7 2 pull-up (note 2) pu17 p7 4 , p7 6 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high notes 1: since p7 0 and p7 1 are n-channel open drain ports, pull-up is not available for them. 2: pull-up is not available for p6 7 and p7 2 , when they are used as i 2 c-bus interface ports. 0 reserved bit must always be set to ? the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 237 rev. 1.0 figure 2.17.26 pull-up control register 2 nothing is assigned. in an attempt to write to these bits, write ?.? the value, if read, turns out to be ?. pull-up control register 2 symbol address when reset pur2 03fe 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu20 p8 2 pull-up pu22 p9 0 , p9 3 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high pu23 p9 4 pull-up 0 0 reserved bit must always be set to ? reserved bits must always be set to ? 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 238 rev. 1.0 table 2.17.1 example connection of unused pins in single-chip mode figure 2.17.27 example connection of unused pins p i n n a m ec o n n e c t i o n p o r t s p 0 , p 2 t o p 1 0 x o u t ( n o t e ) a v c c a f t e r s e t t i n g f o r i n p u t m o d e , c o n n e c t e v e r y p i n t o v s s o r v c c v i a a r e s i s t o r ; o r a f t e r s e t t i n g f o r o u t p u t m o d e , l e a v e t h e s e p i n s o p e n . o p e n c o n n e c t t o v c c n o t e : w i t h e x t e r n a l c l o c k i n p u t t o x i n p i n . c nv s s c o n n e c t v i a r e s i s t o r t o v s s ( p u l l - d o w n ) p o r t p 0 t o p 1 0 ( i n p u t m o d e ) ( i n p u t m o d e ) ( o u t p u t m o d e ) x o u t a v c c m i c r o c o m p u t e r v c c v s s i n s i n g l e - c h i p m o d e o p e n o p e n 0 . 4 7 m f c nv s s M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 239 rev. 1.0 3. usage precaution 3.1 timer a (timer mode) (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff 16 . reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. 3.2 timer a (event counter mode) (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff 16 by under- flow or 0000 16 by overflow. reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. (2) when stop counting in free run type, set timer again. 3.3 timer a (one-shot timer mode) (1) setting the count start flag to 0 while a count is in progress causes as follows: ? the counter stops counting and a content of reload register is reloaded. ? the ta iout pin outputs l level. ? the interrupt request generated and the timer ai interrupt request bit goes to 1. (2) the timer ai interrupt request bit goes to 1 if the timer's operation mode is set using any of the following procedures: ? selecting one-shot timer mode after reset. ? changing operation mode from timer mode to one-shot timer mode. ? changing operation mode from event counter mode to one-shot timer mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. 3.4 timer a (pulse width modulation mode) (1) the timer ai interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures: ? selecting pwm mode after reset. ? changing operation mode from timer mode to pwm mode. ? changing operation mode from event counter mode to pwm mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. (2) setting the count start flag to 0 while pwm pulses are being output causes the counter to stop counting. if the ta iout pin is outputting an h level in this instance, the output level goes to l, and the timer ai interrupt request bit goes to 1. if the taiout pin is outputting an l level in this instance, the level does not change, and the timer ai interrupt request bit does not becomes 1. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 240 rev. 1.0 3.5 timer b (timer mode, event counter mode) (1) reading the timer bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. reading the timer bi register with the reload timing gets ffff 16 . reading the timer bi register after setting a value in the timer bi register with a count halted but before the counter starts counting gets a proper value. 3.6 timer b (pulse period, pulse width measurement mode) (1) if changing the measurement mode select bit is set after a count is started, the timer bi interrupt request bit goes to 1. (2) when the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. 3.7 a-d converter (1) write to each bit (except bit 6) of a-d control register 0, to each bit of a-d control register 1, and to bit 0 of a-d control register 2 when a-d conversion is stopped (before a trigger occurs). in particular, when the vref connection bit is changed from 0 to 1, start a-d conversion after an elapse of 1 m s or longer. (2) when changing a-d operation mode, select analog input pin again. (3) when using a-d converter in the one-shot mode and in the single sweep mode after confirming the completion of a-d conversion, read the a-d register (the completion of a-d con- version is determined by a-d interrupt request bit). (4) when using a-d converter in the repeat mode and in the repeat sweep mode use the main clock without dividing as the internal clock of cpu. (5) the a-d conversion in the sweep mode needs the time as follows; (number of sweep pins + 2 pins) 5 repeat times 5 a-d conversion time for 1 pin. (6) when operating osd or operating data slicer using the h sync and v sync input, do not use the a-d sweap mode (single sweap mode, repeat sweap mode 0, and repeat sweap mode 1). 3.8 stop mode and wait mode ____________ (1) when returning from stop mode by hardware reset, reset pin must be set to l level until main clock oscillation is stabilized. (2) when switching to either wait mode or stop mode, instructions occupying four bytes either from the wait instruction or from the instruction that sets the every-clock stop bit to 1 within the instruction queue are perfected and then the program stops. so put at least four nops in succession either to the wait instruction or to the instruction that sets the every-clock stop bit to 1. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 241 rev. 1.0 3.9 interrupts (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. (3) external interrupt _______ _______ ? when the polarity of the int 0 and int 1 pins is changed, the interrupt request bit is sometimes set to 1. after changing the polarity, set the interrupt request bit to 0. (4) rewrite the interrupt control register ? to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. ? when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 242 rev. 1.0 3.10 built-in prom version 3.10.1 all built-in prom versions high voltage is required to program to the built-in prom. be careful not to apply excessive voltage. be especially careful during power-on. 3.10.2 one time prom version one time prom versions shipped in blank, of which built-in proms are programmed by users, are also provided. for these microcomputers, a programming test and screening are not performed in the as- sembly process and the following processes. to improve their reliability after programming, we recom- mend to program and test as flow shown in figure 3.10.1 before use. figure 3.10.1 programming and test flow for one time prom version p r o g r a m m i n g w i t h p r o m p r o g r a m m e r s c r e e n i n g ( n o t e ) ( l e a v e a t 1 5 0 ? c f o r 4 0 h o u r s ) v e r i f y t e s t p r o m p r o g r a m m e r f u n c t i o n c h e c k i n t a r g e t d e v i c e n o t e : n e v e r e x p o s e t o 1 5 0 ? c e x c e e d i n g 1 0 0 h o u r s . M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 243 rev. 1.0 4. items to be submitted when ordering masked rom version please submit the following when ordering masked rom products. (1) mask rom confirmation form (2) mark specification sheet (3) rom data : eproms (3 sets) *: in the case of eproms, there sets of eproms are required per pattern. *: in the case of floppy disks, 3.5-inch double-sided high-density disk (ibm format) is required per pattern. M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 244 rev. 1.0 table 5.1.1 absolute maximum ratings 5. electrical characteristics 5.1. absolute maximum ratings o p e r a t i n g a m b i e n t t e m p e r a t u r e i n p u t v o l t a g e o u t p u t v o l t a g e v o 0 . 3 t o v c c + 0 . 3 0 . 3 t o v c c + 0 . 3 p d p o w e r d i s s i p a t i o n s t o r a g e t e m p e r a t u r e t a = 2 5 c v c v i t s t g t o p r c m w v 4 0 t o 1 2 5 5 0 0 1 0 t o 7 0 p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 6 7 , p 7 0 , p 7 1 , p 7 2 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 9 3 , p 9 4 , p 1 0 0 , p 1 0 1 , x i n , o s c 1 , r e s e t p a r a m e t e r u n i t a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e 0 . 3 t o 6 . 0 r a t e d v a l u e 0 . 3 t o 6 . 0 v v c o n d i t i o n a v c c v c c s y m b o l c n v s s i n p u t v o l t a g e v i 0 . 3 t o 6 . 0 ( n o t e ) v n o t e : w h e n w r i t i n g t o e p r o m , o n l y c n v s s i s 0 . 3 t o 1 3 ( v ) . p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 6 7 , p 7 0 , p 7 1 , p 7 2 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 9 3 , p 9 4 , p 1 0 0 , p 1 0 1 , r , g , b , o u t 1 , o u t 2 , o s c 2 , x o u t M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 245 rev. 1.0 table 5.2.1 recommended operating conditions (referenced to v cc = 4.5 v to 5.5 v at ta = C 10 o c to 70 o c unless otherwise specified) 5.2 recommended operating conditions 4 . 55 . 5 t y p .m a x . u n i t p a r a m e t e r v c c 5 . 0 s u p p l y v o l t a g e ( n o t e 3 ) s y m b o l m i n s t a n d a r d a n a l o g s u p p l y v o l t a g e ( n o t e 3 ) v c c a v c c v v 0 s u p p l y v o l t a g e v i h v s s 0 . 8 v c cv v c c h i g h i n p u t v o l t a g e v p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 6 7 , p 7 0 , p 7 1 , p 7 2 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 9 3 , p 9 4 , p 1 0 0 , p 1 0 1 , x i n , o s c 1 , r e s e t , c n v s s v i l v 0 . 2 v c c 0 l o w i n p u t v o l t a g e i o h ( a v g ) h i g h a v e r a g e o u t p u t c u r r e n t m a m a i o h ( p e a k ) h i g h p e a k o u t p u t c u r r e n t 5 . 0 1 0 . 0 l o w p e a k o u t p u t c u r r e n t 1 0 . 0 6 . 0 m a f ( x i n ) m a i n c l o c k i n p u t o s c i l l a t i o n f r e q u e n c y m h z l o w a v e r a g e o u t p u t c u r r e n t i o l ( p e a k ) m a i o l ( a v g ) 1 0 p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 6 7 , p 7 0 , p 7 1 , p 7 2 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 9 3 , p 9 4 , p 1 0 0 , p 1 0 1 , r , g , b , o u t 1 , o u t 2 p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 6 7 , p 7 2 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 9 3 , p 9 4 , p 1 0 0 , p 1 0 1 , r , g , b , o u t 1 , o u t 2 p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 6 7 , p 7 2 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 9 3 , p 9 4 , p 1 0 0 , p 1 0 1 , r , g , b , o u t 1 , o u t 2 p 6 7 , p 7 0 t o p 7 2 , p 9 3 , p 9 4 f o s c o s c i l l a t i o n f r e q u e n c y ( f o r o s d ) o s c 1 m h z 2 7 . 0 1 1 . 0 f c v i n i n p u t f r e q u e n c y k h z 1 6 . 2 0 6 1 5 . 7 4 3 l c o s c i l l a t i n g m o d e c e r a m i c o s c i l l a t i n g m o d e 2 4 . 0 v i i n p u t a m p l i t u d e v i d e o s i g n a l h o r i z o n t a l s y n c . s i g n a l o f v i d e o s i g n a l c v i n 1 5 . 2 6 2 v 2 . 5 2 . 0 1 . 5 2 5 . 0 n o t e s 1 : t h e m e a n o u t p u t c u r r e n t i s t h e m e a n v a l u e w i t h i n 1 0 0 m s . 2 : t h e t o t a l i o l ( p e a k ) f o r p o r t s p 0 , p 2 , p 9 , a n d p 1 0 m u s t b e 8 0 m a m a x . t h e t o t a l i o h ( p e a k ) f o r p o r t s p 0 , p 2 , p 9 , a n d p 1 0 m u s t b e 8 0 m a m a x . t h e t o t a l i o l ( p e a k ) f o r p o r t s p 3 , p 4 , p 5 , p 6 , p 7 a n d p 8 2 m u s t b e 8 0 m a m a x . t h e t o t a l i o h ( p e a k ) f o r p o r t s p 3 , p 4 , p 5 , p 6 , p 7 2 , p 7 4 , p 7 6 , a n d p 8 2 m u s t b e 8 0 m a m a x . 3 : c o n n e c t 0 . 1 m f o r m o r e c a p a c i t o r e x t e r n a l l y b e t w e e n t h e p o w e r s o u r c e p i n s v c c v s s a n d a v c c v s s s o a s t o r e d u c e p o w e r s o u r c e n o i s e . a l s o c o n n e c t 0 . 1 m f o r m o r e c a p a c i t o r e x t e r n a l l y b e t w e e n t h e p o w e r s o u r c e p i n s v c c c n v s s . 5 . 0 l o w a v e r a g e o u t p u t c u r r e n t m a i o l ( a v g ) p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 1 0 0 , p 1 0 1 , r , g , b , o u t 1 , o u t 2 p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 6 7 , p 7 0 , p 7 1 , p 7 2 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 9 3 , p 9 4 , p 1 0 0 , p 1 0 1 , x i n , o s c 1 , r e s e t , c n v s s M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 246 rev. 1.0 table 5.3.1 electrical characteristics (referenced to v cc = 5 v, v ss = 0 v at ta = 25 o c, f(x in ) = 10 mhz unless otherwise specified) 5.3 electrical characteristics h i g h p o w e r l o w p o w e r h i g h p o w e r l o w p o w e r s y m b o l v o h v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e l o w o u t p u t v o l t a g e v o l l o w o u t p u t v o l t a g e v o l h y s t e r e s i s h y s t e r e s i s h y s t e r e s i s h i g h i n p u t c u r r e n t i i h h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e v t + - v t - v t + - v t - v t + - v t - m e a s u r i n g c o n d i t i o n x o u t x o u t x i n p a r a m e t e r i o h = 5 m a i o h = 1 m a i o h = 2 0 0 m a i o h = 0 . 5 m a i o l = 5 m a i o l = 1 m a i o l = 6 . 0 m a i o l = 0 . 5 m a p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 6 7 , p 7 2 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 9 3 , p 9 4 , p 1 0 0 , p 1 0 1 , r , g , b , o u t 1 , o u t 2 p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 1 0 0 , p 1 0 1 , r , g , b , o u t 1 , o u t 2 p 6 7 , p 7 0 t o p 7 2 , p 9 3 , p 9 4 p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3 , p 5 0 , p 5 2 , p 5 3 , p 5 5 r e s e t p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 6 7 , p 7 0 , p 7 1 , p 7 2 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 9 3 , p 9 4 , p 1 0 0 , p 1 0 1 x i n , r e s e t , c n v s s , o s c 1 v i = 5 v s t a n d a r d t y p . u n i t v v 4 . 7 v 3 . 0 3 . 0 v 2 . 0 0 . 6v v 2 . 0 2 . 0 0 . 20 . 8v 0 . 21 . 8v 0 . 20 . 8v 5 . 0 m a m i n .m a x . 3 . 0 l o w i n p u t c u r r e n t i i l v i = 0 v p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 6 7 , p 7 0 , p 7 1 , p 7 2 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 9 3 , p 9 4 , p 1 0 0 , p 1 0 1 x i n , r e s e t , c n v s s , o s c 1 m a 5 . 0 l o w o u t p u t v o l t a g e v o l i o l = 2 0 0 m a p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3 , p 5 0 , p 5 2 , p 5 3 , p 5 5 0 . 4 5v t b 0 i n , i n t 0 , i n t 1 , c l k 0 , c l k 2 , s c l 1 , s c l 2 , s c l 3 , s d a 1 , s d a 2 , s d a 3 , h s y n c , v s y n c , h c 0 , h c 1 , r x d 0 , r x d 2 f ( x i n ) = 1 0 m h z s q u a r e w a v e , n o d i v i s i o n f ( x i n ) = 1 0 m h z s q u a r e w a v e , d i v i s i o n b y 8 p u l l - u p r e s i s t o r p p u l l u p i c c p o w e r s u p p l y c u r r e n t t a = 2 5 c w h e n c l o c k i s s t o p p e d t a = 7 0 c w h e n c l o c k i s s t o p p e d i n s i n g l e - c h i p m o d e , t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e v s s v i = 0 v p 0 0 t o p 0 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3, p 5 0 , p 5 2 , p 5 3 , p 5 5 , p 6 2 , p 6 3 , p 6 7 , p 7 2 , p 7 4 , p 7 6 , p 8 2 , p 9 0 , p 9 3 , p 9 4 3 05 0 1 0m a 1 0 m a m a 2 0 0 7 09 0 o s d o n , d a t a s l i c e r o n o s d o f f , d a t a s l i c e r o f f o s d o f f , d a t a s l i c e r o f f r b s i 2 c - b u s b u s s w i t c h c o n n e c t i o n r e s i s t o r ( b e t w e e n s c l 1 a n d s c l 2 , s d a 1 a n d s d a 2 ) v c c = 4 . 5 v1 3 0 w r f xi n f e e d b a c k r e s i s t o r x i n 1 . 0 m w r f xc i n f e e d b a c k r e s i s t o r x c i n 6 . 0 m w k w 1 6 7 . 0 5 0 . 0 3 0 . 0 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 247 rev. 1.0 5.4 a-d conversion characteristics table 5.4.1 a-d conversion characteristics (referenced to v cc = av cc = 5v, v ss = av ss = 0 v at ta = 25 o c, f(x in ) = 10 mhz unless otherwise specified) 5.5 d-a conversion characteristics table 5.5.1 d-a conversion characteristics (referenced to v cc = 5v, v ss = av ss = 0v at ta = 25 o c, f(x in ) = 10 mhz unless otherwise specified) note: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converters ladder resistance is not included. also, when the vref is unconnected at the a-d control register, i vref is sent. 5.6 analog r, g, b output characteristics table 5.6.1 analog r, g, b output characteristics (v cc = 5v, v ss = 0v at ta = 25 o c, f(x in ) = 10 mhz unless otherwise specified) standard min. typ. max. resolution absolute accuracy bits lsb v ref = v cc 5 8 symbol parameter measuring condition unit v ref = v cc = 5 v r ladder ladder resistance reference voltage analog input voltage k w v v ia v ref v 0 10 v cc v cc 40 conversion time m s 2.8 t conv t samp sampling time 0.3 m s v ref = v cc sample & hold function not available sample & hold function available (8 bit) v ref = v cc = 5 v 5 lsb min. typ. max. t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % k w ma i vref 10 1.5 8 3 symbol parameter measuring condition unit 20 10 4 m s ( note ) standard max. min. output impedance output deviation k w v ns r o v oe t st parameter symbol unit standard 0.5 50 2 test conditions settling time load capacity of 10 pf, load resistance of 20 k w , 70 % dc level M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 248 rev. 1.0 table 5.7.1 external clock input (referenced to v cc = 5 v, v ss = 0 v at ta = 25 o c unless otherwise specified) 5.7 timing requirements max. min. external clock input cycle time external clock input high pulse width external clock input low pulse width ns ns ns t c t w(h) t w(l) parameter symbol unit standard 100 40 40 t r t f external clock rise time external clock fall time 15 15 ns ns table 5.7.2 timer b input (counter input in event counter mode) (referenced to v cc = 5 v, v ss = 0 v at ta = 25 o c unless otherwise specified) table 5.7.3 timer b input (pulse period measurement mode) (referenced to v cc = 5 v, v ss = 0 v at ta = 25 o c unless otherwise specified) table 5.7.4 timer b input (pulse width measurement mode) (referenced to v cc = 5 v, v ss = 0 v at ta = 25 o c unless otherwise specified) standard max. min. tb0 in input cycle time (counted on one edge) tb0 in input high pulse width (counted on one edge) tb0 in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tb0 in input high pulse width (counted on both edges) tb0 in input low pulse width (counted on both edges) tb0 in input cycle time (counted on both edges) 100 40 40 80 80 200 standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tb0 in input high pulse width tb0 in input cycle time tb0 in input low pulse width 400 200 200 standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tb0 in input cycle time tb0 in input high pulse width tb0 in input low pulse width 400 200 200 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 249 rev. 1.0 _______ table 5.7.6 external interrupt inti inputs (referenced to v cc = 5 v, v ss = 0 v at ta = 25 o c unless otherwise specified) table 5.7.5 serial i/o (referenced to v cc = 5 v, v ss = 0 v at ta = 25 o c unless otherwise specified) ns ns ns ns ns ns ns standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 200 100 100 0 30 90 80 standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width 250 250 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 250 rev. 1.0 figure 5.8.1 timing diagram 5.8 timing diagram t su(d?) tb0 in input clk i txd i rxd i t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c?) t h(c?) t h(c?) int i input M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 251 rev. 1.0 6. mask confirmation form gzz sh56 45b <93a0> mitsubishi electric single-chip 16-bit microcomputer M306V5ME-XXXSP mask rom confirmation form mask rom number note : please complete all items marked . checksum code for total eprom area : (hex) (1) the area from 00000 16 to 0000f 16 is for storing data on the product type name. the ascii code for 'm306v5me-' is shown at right. the data in this table must be written to address 00000 16 to 0000f 16 . both address and data are shown in hex. (2) write ?f 16 to the lined area. ' m ' = 4d 16 00000 16 00001 16 00002 16 00003 16 00004 16 00005 16 00006 16 00007 16 address ' ? ' = 2d 16 00008 16 00009 16 0000a 16 0000b 16 0000c 16 0000d 16 0000e 16 0000f 16 address eprom type : ' 0 ' = 30 16 ' 6 ' = 36 16 ' v ' = 56 16 ' 5 ' = 35 16 ' m ' = 4d 16 ' e ' = 45 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ' 3 ' = 33 16 supervisor signature receipt date : section head signature customer company name date issued date : tel ( ) issuance signature submitted by supervisor 1. check sheet 27c401 address 00000 16 product : area containing ascii code for m306v5me - rom(192k) 0000f 16 00010 16 0ffff 16 50000 16 7ffff 16 name the product you order, and choose which to give in, eproms or floppy disks. if you order by means of eproms, three sets of eproms are required per pattern. if you order by means of floppy disks, one floppy disk is required per pattern. mitsubishi will create the mask using the data on the eproms supplied, providing the data is the same on at least two of those sets. mitsubishi will, therefore, only accept liability if there is any discrepancy between the data on the eprom sets and the rom data written to the product. please carefully check the data on the eproms being submitted to mitsubishi. in the case of eproms 30000 16 10000 16 osd rom (1/4) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 252 rev. 1.0 20400 20401 20600 20601 213f8 213f9 213fc 213fd 21400 21401 21600 21601 223f8 223f9 223fc 223fd 22400 22401 22600 22601 233f8 233f9 233fc 233fd 23400 23401 23600 23601 243f8 243f9 243fc 243fd 24400 24401 24600 24601 253f8 253f9 253fc 253fd 25400 25401 25600 25601 263f8 263f9 263fc 263fd 26400 26401 26600 26601 273f8 273f9 273fc 273fd 27400 27401 27600 27601 283f8 283f9 283fc 283fd 28400 28401 28600 28601 293f8 293f9 293fc 293fd 29400 29401 29600 29601 2a3f8 2a3f9 2a3fc 2a3fd 2a400 2a401 2a600 2a601 21bf8 21bf9 21bfc 21bfd 2b400 2b401 2b600 2b601 22bf8 22bf9 22bfc 22bfd 2c400 2c401 2c600 2c601 23bf8 23bf9 23bfc 23bfd 2d400 2d401 2d600 2d601 24bf8 24bf9 24bfc 24bfd 2e400 2e401 2e600 2e601 25bf8 25bf9 25bfc 25bfd 2f400 2f401 2f600 2f601 26bf8 26bf9 26bfc 26bfd 20c00 20c01 20e00 20e01 27bf8 27bf9 27bfc 27bfd 21c00 21c01 21e00 21e01 28bf8 28bf9 28bfc 28bfd 22c00 22c01 22e00 22e01 29bf8 29bf9 29bfc 29bfd 23c00 23c01 23e00 23e01 2abf8 2abf9 2abfc 2abfd 24c00 24c01 24e00 24e01 25c00 25c01 25e00 25e01 26c00 26c01 26e00 26e01 27c00 27c01 27e00 27e01 28c00 28c01 28e00 28e01 29c00 29c01 29e00 29e01 2ac00 2ac01 2ae00 2ae01 2bc00 2bc01 2be00 2be01 2cc00 2cc01 2ce00 2ce01 2dc00 2dc01 2de00 2de01 2ec00 2ec01 2ee00 2ee01 2fc00 2fc01 2fe00 2fe01 10000 10800 10001 10801 11000 11800 11001 11801 12000 12800 12001 12801 13000 13800 13001 13801 14000 14800 14001 14801 15000 15800 15001 15801 16000 16800 16001 16801 17000 17800 17001 17801 18000 18800 18001 18801 19000 19800 19001 19801 1a000 1a800 1a001 1a801 1b000 1b800 1b001 1b801 1c000 1c800 1c001 1c801 1d000 1d800 1d001 1d801 1e000 1e800 1e001 1e801 1f000 1f800 1f001 1f801 100fe 100ff 101fe 101ff 102fe 102ff 103fe 103ff 104fe 104ff 105fe 105ff 106fe 106ff 107fe 107ff 108fe 108ff 109fe 109ff 10afe 10aff 10bfe 10bff 10cfe 10cff 10dfe 10dff 10efe 10eff 10ffe 10fff 110fe 110ff 111fe 111ff 112fe 112ff 113fe 113ff 114fe 114ff 115fe 115ff 116fe 116ff 117fe 117ff 118fe 118ff 119fe 119ff 120fe 120ff 121fe 121ff 122fe 122ff 123fe 123ff 124fe 124ff 125fe 125ff 126fe 126ff 127fe 127ff 128fe 128ff 129fe 129ff 12afe 12aff 12bfe 12bff 12cfe 12cff 12dfe 12dff 12efe 12eff 12ffe 12fff 130fe 130ff 131fe 131ff 132fe 132ff 133fe 133ff 134fe 134ff 135fe 135ff 136fe 136ff 137fe 137ff 138fe 138ff 139fe 139ff 140fe 140ff 141fe 141ff 142fe 142ff 143fe 143ff 144fe 144ff 145fe 145ff 146fe 146ff 147fe 147ff 148fe 148ff 149fe 149ff 14afe 14aff 14bfe 14bff 14cfe 14cff 14dfe 14dff 14efe 14eff 14ffe 14fff 150fe 150ff 151fe 151ff 152fe 152ff 153fe 153ff 154fe 154ff 155fe 155ff 156fe 156ff 157fe 157ff 158fe 158ff 159fe 159ff 160fe 160ff 161fe 161ff 162fe 162ff 163fe 163ff 164fe 164ff 165fe 165ff 166fe 166ff 167fe 167ff 168fe 168ff 169fe 169ff 16afe 16aff 16bfe 16bff 16cfe 16cff 16dfe 16dff 16efe 16eff 16ffe 16fff 170fe 170ff 171fe 171ff 172fe 172ff 173fe 173ff 174fe 174ff 175fe 175ff 176fe 176ff 177fe 177ff 178fe 178ff 179fe 179ff 18002 18003 18102 18103 18202 18203 18302 18303 18402 18403 18502 18503 18602 18603 18702 18703 18802 18803 18902 18903 18a02 18a03 18b02 18b03 18c02 18c03 18d02 18d03 18e02 18e03 18f02 18f03 19002 19003 19102 19103 19202 19203 19302 19303 19402 19403 19502 19503 19602 19603 19702 19703 19802 19803 19902 19903 1a002 1a003 1a102 1a103 1a202 1a203 1a302 1a303 1a402 1a403 1a502 1a503 1a602 1a603 1a702 1a703 1a802 1a803 1a902 1a903 1aa02 1aa03 1ab02 1ab03 1ac02 1ac03 1ad02 1ad03 1ae02 1ae03 1af02 1af03 1b002 1b003 1b102 1b103 1b202 1b203 1b302 1b303 1b402 1b403 1b502 1b503 1b602 1b603 1b702 1b703 1b802 1b803 1b902 1b903 1c002 1c003 1c102 1c103 1c202 1c203 1c302 1c303 1c402 1c403 1c502 1c503 1c602 1c603 1c702 1c703 1c802 1c803 1c902 1c903 1ca02 1ca03 1cb02 1cb03 1cc02 1cc03 1cd02 1cd03 1ce02 1ce03 1cf02 1cf03 1d002 1d003 1d102 1d103 1d202 1d203 1d302 1d303 1d402 1d403 1d502 1d503 1d602 1d603 1d702 1d703 1d802 1d803 1d902 1d903 1e002 1e003 1e102 1e103 1e202 1e203 1e302 1e303 1e402 1e403 1e502 1e503 1e602 1e603 1e702 1e703 1e802 1e803 1e902 1e903 1ea02 1ea03 1eb02 1eb03 1ec02 1ec03 1ed02 1ed03 1ee02 1ee03 1ef02 1ef03 1f002 1f003 1f102 1f103 1f202 1f203 1f302 1f303 1f402 1f403 1f502 1f503 1f602 1f603 1f702 1f703 1f802 1f803 1f902 1f903 (3) be sure to store ?f 16 ?in the following test font addresses in osd rom. when producing osd rom data with the osd font editor program of mitsubishi, ?f 16 ?is set automatically to these test font addresses. (2/4) gzz sh56 45b <93a0> mitsubishi electric single-chip 16-bit microcomputer M306V5ME-XXXSP mask rom confirmation form mask rom number (all addresses below are shown in hex.) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 253 rev. 1.0 gzz sh56 45b <93a0> mitsubishi electric single-chip 16-bit microcomputer M306V5ME-XXXSP mask rom confirmation form mask rom number note: the rom cannot be processed if the type no. written to the eprom does not match the type no. in the check sheet. the ascii code for the type no. can be written to eprom addresses 00000 16 to 0000f 16 by specifying the pseudo-instructions shown in the following table at the beginning of the assembler source program. the mark specification differs according to the type of package. after entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to mitsubishi. for the M306V5ME-XXXSP, submit the 64p4b mark specification sheet. 2. mark specification eprom type code entered in source program 27c401 .section asciicode, rom data .org 080000h .byte ' m306v5me- ' mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the rom data to be burned into products we produce. check thoroughly the contents of the mask files you give in. prepare 3.5 inches 2hd(ibm format) floppy disks. and store only one mask file in a floppy disk. in the case of floppy disks file code : (hex) mask file name : .msk (alpha-numeric 8-digit) (3/4) note: when using the floppy disks, do not store the type no. to addresses 0000 16 to 0000f 16 . M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 254 rev. 1.0 gzz sh56 45b <93a0> mitsubishi electric single-chip 16-bit microcomputer M306V5ME-XXXSP mask rom confirmation form mask rom number 4. special item (indicate none if there is no specified item) 3. usage conditions for our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) which kind of x in -x out oscillation circuit is used? ceramic resonator quartz-crystal oscillator external clock input other ( ) what frequency do you use? f(x in ) = mh z (2) which operation mode do you use? single-chip mode memory expansion mode microprocessor mode thank you cooperation. (4/4) M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 255 rev. 1.0 7. mark specification form M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 256 rev. 1.0 8. one time prom version m306v5eesp marking m306v5eesp xxxxxxx xxxxxxx is mitsubishi lot number M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 257 rev. 1.0 9. package outline 64 33 32 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d sdip64-p-750-1.78 weight(g) 7.9 jedec code eiaj package code lead material alloy 42/cu alloy 64p4b plastic 64pin 750mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.38 ?.8 0.4 0.5 0.59 0.9 1.0 1.3 0.65 0.75 1.05 0.2 0.25 0.32 56.2 56.4 56.6 16.85 17.0 17.15 1.778 19.05 2.8 0 ?5 5.08 e e 1 mmp M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 258 rev. 1.0 structure of register refer to the figure below as for each register. v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e < e x a m p l e > b i t a t t r i b u t e s ( n o t e 1 ) ( n o t e 2 ) p r o c e s s o r m o d e r e g i s t e r 1 ( n o t e ) s y m b o la d d r e s sw h e n r e s e t p m 10 0 0 5 1 6 0 0 0 0 0 x 0 0 2 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . r e s e r v e d b i t m u s t a l w a y s b e s e t t o 0 0 p m 1 7 w a i t b i t 0 : n o w a i t s t a t e 1 : w a i t s t a t e i n s e r t e d r e s e r v e d b i t s m u s t a l w a y s b e s e t t o 0 00 0 : b i t i n w h i c h n o t h i n g i s a s s i g n e d 2 : b i t a t t r i b u t e s ? ? ? ? ? ? t h e a t t r i b u t e s o f c o n t r o l r e g i s t e r b i t s a r e c l a s s i f i e d i n t o 3 t y p e s : r e a d - o n l y , w r i t e - o n l y a n d r e a d a n d w r i t e . i n t h e f i g u r e , t h e s e a t t r i b u t e s a r e r e p r e s e n t e d a s f o l l o w s : n o t e s 1 : v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 a f t e r r e s e t r e l e a s e 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 a f t e r r e s e t r e l e a s e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i n d e t e r m i n a t e a f t e r r e s e t r e l e a s e 5 b i t i n w h i c h n o t h i n g i s a s s i g n e d r e a d e n a b l e d 5 r e a d d i s a b l e d b i t i n w h i c h n o t h i n g i s a s s i g n e d ( t h e r e a d v a l u e i s i n d e t e r m i n a t e u n l e s s o t h e r w i s e m e n t i o n e d . ) r r e a d w w r i t e w r i t e e n a b l e d 5 w r i t e d i s a b l e d b i t i n w h i c h n o t h i n g i s a s s i g n e d 0 1 r e s e r v e d b i t m u s t a l w a y s b e s e t t o 1 n o t e : a s b i t 1 o f t h i s r e g i s t e r b e c o m e s 0 a t r e s e t , m u s t a l w a y s b e s e t t o 1 a f t e r r e s e t r e l e a s e . s e t b i t 1 o f t h e p r o t e c t r e g i s t e r ( a d d r e s s 0 0 0 a 1 6 ) t o 1 w h e n w r i t i n g n e w v a l u e s t o t h i s r e g i s t e r . M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 259 rev. 1.0 [a] a-d conversion interrupt control register (adic) ...................................................................... 43 address match interrupt enable register (aier) ...................................................................... 53 address match interrupt register i (rmadi) .. 53 a-d register i (adi) ...................................... 141 a-d control register 2 (adcon2) ................ 141 a-d control register 1 (adcon1) ...................... ............................ 140, 143, 145, 147, 149, 150 a-d control register 0 (adcon0) ............................ 140, 143, 145, 147, 149, 151 [b] block control register i (bci) ....................... 171 bottom border control register (bbr) .......... 215 bus collision detection interrupt control register (bcnic) ....................................................... 43 [c] caption data register i (cdi) ......................... 13 caption position register (cps) .................. 161 clock control register (cs) .......................... 179 clock run-in detect register (crd) .............. 162 color palette register i (cri) ....................... 119 count start flag (tabsr) ........................ 71, 81 [d] d-a control register (dacon) ..................... 154 d-a register i (dai) ...................................... 154 data clock position register (dps) .............. 163 data slicer control register 1 (dsc1) .......... 157 data slicer control register 2 (dsc2) .......... 157 data slicer interrupt control register (dsic) .. 43 data slicer reserved register i (dri) ............ 164 dma0 request cause select register (dm0sl) ...................................................................... 60 dma1 request cause select register (dm1sl) .. ...................................................................... 61 dmai control register (dmicon) ................... 61 dmai interrupt control register (dmiic) ......... 43 ------register index------ dmai destination pointer (dari) ................... 62 dmai transfer counter (tcri) ....................... 62 dmai source pointer (sari) .......................... 62 [h] horizontal position register (hp) ................. 176 h sync counter register (hc) ....................... 165 h sync counter latch ...................................... 13 [i] i 2 ci data shift register (iicis0) .................... 123 i 2 ci address register (iicis0d) ................... 124 i 2 ci status register (iicis1) ......................... 131 i 2 ci control register (iicis1d) ..................... 128 i 2 ci clock control register (iicis2) ............... 126 i 2 ci port selection register (iicis2d) ........... 121 i 2 ci transmit buffer register (iicis0s) ......... 123 i/o polarity control register (pc) ................. 180 interrupt control reserved register i (reiic) ......... 52 interrupt request cause select register (ifsr) ...................................................................... 52 inti interrupt control register (intiic) ........... 43 [l] left border control register (lbr) ............... 216 [m] multi-master i 2 c-bus interface i interrupt control register (iiciic) .................................. 43 [o] one-shot start flag (onsf) ........................... 72 osd control register 1 (oc1) ...................... 170 osd control register 2 (oc2) ...................... 173 osd control register 3 (oc3) ...................... 198 osd control register 4 (oc4) ...................... 182 osd reserved register i (ori) ..................... 220 osdi interrupt control register (osdiic) ........ 43 [p] peripheral mode register (pm) ...................... 87 M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller 260 rev. 1.0 port p0, p2, p3 register (p0 to p0, p2, p3) ....................................... 231 port p0, p2, p3 direction register (pd0, pd2, pd3) ......................................... 227 port p4 register (p4) ................................... 231 port p4 direction register (pd4) .................. 227 port p5 register (p5) ................................... 232 port p5 direction register (pd5) .................. 228 port p6 register (p6) ................................... 232 port p6 direction register (pd6) .................. 228 port p7 register (p7) ................................... 233 port p7 direction register (pd7) .................. 229 port p8 register (p8) ................................... 233 port p8 direction register (pd8) .................. 229 port p9 register (p9) ................................... 234 port p9 direction register (pd9) .................. 230 port p10 register (p10) ............................... 234 port p10 direction register (pd10) .............. 230 port reserved register i (pri) ...................... 235 processor mode register 0 (pm0) ................. 23 processor mode register 1 (pm1) ................. 23 protect register (prcr) ................................ 35 pull-up control register 0 (pur0) ................ 236 pull-up control register 1 (pur1) ................ 236 pull-up control register 2 (pur2) ................ 237 [r] raster color register (rsc) ......................... 217 reserved register i (invci) ............... 73, 81, 86 right border control register (rbr) ............ 216 [s] sprite horizontal position register (hs) .... 212 sprite osd control register (sc) ............. 211 sprite vertical position register i (vsi) ..... 212 system clock control register 0 (cm0) .......... 30 system clock control register 1 (cm1) .......... 30 [t] timer ai interrupt control register (taiic) ...................................................................... 43 timer bi interrupt control register (tbiic) ...................................................................... 43 timer ai register (tai) ................................... 71 timer bi register (tbi) ................................... 81 timer ai mode register (taimr) .............................................. 70, 74, 76, 77, 78 timer bi mode register (tbimr) .................................................... 80, 82, 83, 84 top border control register (tbr) ............... 215 trigger select register (trgsr) ................... 73 [u] uart transmit/receive control register 2 (ucon) ...................................................................... 97 uart0 transmit/receive control register 0 (u0c0) ...................................................................... 94 uart0 transmit/receive control register 1 (u0c1) ...................................................................... 96 uart0 transmit/receive mode register (u0mr) ...................................................... 93, 100, 107 uart2 special mode register (u2smr) ........... 97 uart2 transmit/receive mode register (u2mr) ...................................................... 93, 100, 107 uart2 transmit/receive control register 0 (u2c0) ...................................................................... 95 uart2 transmit/receive control register 1 (u2c1) ...................................................................... 96 uarti bit rate generator (uibrg) ................ 92 uarti receive buffer register (uirb) ............ 92 uarti receive interrupt control register (siric) ...................................................................... 43 uarti transmit buffer register (uitb) ........... 92 uarti transmit interrupt control register (sitic) ...................................................................... 43 up/down flag (udf) ...................................... 72 [v] v sync interrupt control register (vsyncic) ........ 43 vertical position register i (vpi) ................... 176 [w] watchdog timer control register (wdc) ........ 57 watchdog timer start register (wdts) .......... 57 ? 1999 mitsubishi electric corp. new publication, effective june. 2000. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that c ustomers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). ? when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herei n for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with a ppropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. head office: 2-2-3, marunouchi, chiyoda-ku, tokyo 100-8310, japan M306V5ME-XXXSP m306v5eesp mitsubishi microcomputers single-chip 16-bit cmos microcomputer with closed caption decoder and on-screen display controller rev. rev. no. date 1.0 first edition of pdf file 0006 (1/1) revision description revision history M306V5ME-XXXSP, m306v5eesp (rev.1.0) data sheet |
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